With the tools, the company claims, designers will be able to use C-language code to drive the exploration of different instruction sets and architectures, rather than select an established core and then write software for that core. The tools will let designers recompile their code for a number of custom architectures and run simulations before selecting and synthesizing an application-specific, DSP-like processor.

And, according to Target, because application-specific instruction processors can be matched precisely to requirements, they can cut IC power consumption by up to 90 percent and die area by half, compared with conventional general-purpose solutions.

The Chess/Checkers tools have been undergoing alpha and beta test with a number of customers since 1997. Motorola has designed and programmed a new application-specific processor for GSM speech coding using the tools, the company said.

The Chess/Checkers environment consists of a C compiler called Chess, a linker called Bridge, an instruction-set-simulator called Checkers and an assembler and disassembler called Darts. In contrast with other DSP support tools, Chess/Checkers is a retargetable environment.

Designers can specify the behavior of their application-specific DSP in a high-level processor description language designated nML.

Low-level code
Once an nML file specifies the target processor, Chess reads the file to generate low-level code from C-language software. Similarly, Checkers uses the file to accept the low-level code and simulate its running on the target processor.

"Until recently, tool support was only considered after the microprocessor architecture was finished," said Gert Goossens, general manager of Target. "With Chess/Checkers, tools are available right from the beginning of the architectural design process. Designers can perform true architectural exploration by trying out alternative architectures in nML and evaluating their performance by running the retargetable compiler and instruction-set simulator."

While most of Target's re-targetable technology comes from IMEC, a first version of the nML language was developed at the Technical University of Berlin. "Experience shows that nML is quickly accepted by architecture designers and programmers who are used to writing assembly code," Goossens said.

"The early use of the tools during the architecture-design phase naturally leads to an architecture that is well-suited to the Chess compiler," he said. "The compiler also uses novel algorithmic optimizations that improve the code quality. As a result, large applications can be implemented completely from C specs and the resulting code quality is comparable to manually optimized code."

Chess provides specific support for DSPs that feature heavily encoded instructions and a heterogeneous register set. The compiler assumes time-stationary coding and that every instruction executes in a single cycle. This allows the processing pipeline to be fully controlled by the software that is generated by the Chess compiler and reduces the complexity of DSP control logic.