Cadence will also make public new information about its Felix initiative, which addresses hardware/software codesign before partitioning occurs. The company will announce delivery of the first virtual-component codesign (VCC) products to its Felix-initiative partners.

Mentor Graphics Corp. (Wilsonville, Ore.) has upgraded its Seamless CVE product to support CPUs and DSPs commu-nicating via shared memory. Deals with Motorola, DSP Group and Wind River Systems will increase Mentor's processor and real-time operating system (RTOS) support. Synopsys Inc. (Mountain View, Calif.) is announcing debugging support from Mentor's Microtec division for the Synopsys Eagle product, along with Advanced RISC Machines (ARM) model support.

All of these companies are addressing a market that's growing explosively as the need for software and hardware integration increases. Gary Smith, principal EDA analyst at Dataquest Inc. here, said hardware/software coverification will soar from $14 million last year to more than $60 million in 2002.

Smith said that Mentor and Synopsys are running "neck and neck" and hold nearly the entire market, though Summit Design Automation (Beaverton, Ore.) is trying to make inroads with its V-CPU product.

Cadence signaled its intent in March, when it announced an agreement to acquire coverification technology from Motorola Semiconductor Products Sector (Austin, Texas). Cadence is now announcing the Affirma hardware/software product, which is shipping this quarter on Unix platforms.

The Affirma HW/SW Verifier consists of three components: an open API for integrating models and debuggers, communications management between software debuggers and HDL simulation and integration with Affirma HDL simulators and the SimVision debugging environment. The product can also take in Object Model Interface (OMI) test benches generated by Cadence's SPW and Bones products.

The coverification products from Cadence, Mentor, Synopsys and Summit are all based on the same general concept. They let designers run software debuggers or instruction-set simulators in concert with HDL simulation, which represents hardware that's not yet built. Thus, software development and combined software/hardware debugging can take place before a physical prototype is ready.

John Murphy, marketing group director for Cadence's design and verification business unit, said the Affirma product has two key advantages. One is its integration with Cadence's Inca-based simulation technology, which includes both VHDL and Verilog, and offers both event-driven and cycle-based simulation. Another is a promised integration with the forthcoming Felix codesign tools.

But Cadence is well behind Mentor and Synopsys when it comes to support for debuggers, models and HDL simulators. Cadence is working on support for Wind River's VxWorks RTOS and Tornado development environment and is announcing support for ARM-7 and Motorola HC08 and HC12 processors. HDL simulation can come from Cadence only.

Mentor, in contrast, has RTOS and debugging support from its own Microtec division and from Green Hills, and is adding Wind River at this week's conference. Mentor's Seamless CVE offers bus-interface and instruction-set models for such processors as ARM, PowerPC, LSI Logic RISC, Coldfire and Intel 960, and is adding Motorola M-Core and DSP Group SmartCore support.

Seamless CVE version 3.0, announced this week, greatly expands the product's DSP support. Jim Kinney, product marketing manager for Seamless, noted that the product has a "coherent memory server" that speeds up processor execution. That server has been enhanced with more optimizations for DSPs, and it can now support two processors, such as a DSP and a CPU, communicating through shared memory.

Synopsys competes with Mentor in coverification, but Mentor's Microtec division is also a major supplier of debugging tools with its Xray product. Thus, Synopsys this week is announcing a partnership with Mentor to support Xray with Synopsys' Eagle system. "Microtec has a reasonable market share, and we have common customers," said Geoff Bunza, Synopsys director of engineering.

Synopsys last week announced its support for ARM cores, including the ARM7 and ARM9. The partnership agreement is intended to support both existing and future cores, Bunza said. Like Mentor, Synopsys supports a variety of third-party debugging environments and offers models for many popular CPUs and DSPs.

While coverification takes place after hardware/software partitioning, Cadence's Felix initiative reaches into the design cycle much earlier. That company's VCC software lets designers capture and simulate system behavior, capture system architecture, map behavior into architecture, run performance simulations with architectural constraints, and explore hardware/software design trade-offs.

At present, VCC is available only to the Felix industrial partners. "Because it's new technology and a perceived paradigm shift, we really have to spend some time with a limited number of people to make them successful," said Misha Burich, vice-president of R&D for codesign at Cadence. "We suspect it will be eight to 12 months before we can open it up for general consumption."

Felix project partners include ARM, BMW, Debis Systemhaus, Ericsson, Magnetic Marelli, Motorola, National Semiconductor and STMicroelectronics.

As revealed at a recent System-Level Design Workshop, the Felix project has involved some work with the hybrid Esterel-C language. But Burich emphasized VCC software will support multiple languages and models of computation. Unlike existing system-level products such as SPW and Bones, VCC will support both data-flow and control-oriented systems — and will map behavior or algorithms into architecture, a step missing from most high-level design tools.