"As a zealot designer myself, the ability to build your own chips is just Disneyland," said John Birkner, vice president and cofounder of QuickLogic Corp. "We've seen programmable logic making steady inroads into the [normal] uses of logic."

Some of the papers to be presented at PLDCon underscore that trend. Birkner will be demonstrating how an FPGA, thanks to the addition of embedded RAM, can be used to build a FIFO whose mean time between failures is significantly better than that of off-the-shelf parts. Kenneth Smith, an ASIC designer for Hewlett-Packard Co.'s LaserJet printer division, will explain using an FPGA as a "stethoscope" to monitor an embedded processor core. And Glenn Baxter of Xilinx Inc. will demonstrate how FPGAs can build "intelligent peripherals," chips that perform some or all of a system's software function, much as 3-D graphics accelerators do.

Smith and colleague Erick Pew started the stethoscope project in hopes of providing real-time debugging for a particular ASIC. What made an FPGA suitable for the task was the increase in speeds for the parts — Smith needed to operate at more than 33 MHz. "By PLD standards, that's screaming. Especially since this was about a year ago November when we kicked off the design," he said. "Without that, there's just no way you could pull off something like that with a PLD."

The availability of embedded RAM has also provoked new uses for programmable logic, said Birkner, who exploited that capability in building his FIFO. "We have embraced the system on a chip, and memory was one of the last things that we needed, to give us all the pieces," Birkner said.

Another key to programmable logic's expanding role has been the tool set.

"The tools have matured quite well," Birkner said. It's been observed that the ideal tool sets described by academicians and by designers in the trenches have finally begun to match, a sign that the industry is zeroing in on what it truly needs.

Generally, the agreement is that designs should begin in HDL, followed by some amount of simulation to verify the design is credible. Static timing analysis should follow, to discover the worst-case paths in the design.

"My passion for the future of tools is probably similar to what anyone would expect, and that's to get into more graphical interfaces," Birkner said.