Designers can control their destiny by spinning their own FIFO design, using embedded dual-port RAMs in FPGAs. The dual-port feature is crucial in separating the write side of the RAM from the read, both architecturally and in time. Dual-port, as the name implies, separates both address and data from write and read operations. Any word in the RAM can be written simultaneously with the read operation of any other word. In a synchronous FIFO design, dual-port RAM is used for independent PUSH and POP operation with a common clock. Write data is pushed in the clock period that PUSH is asserted. Read data is popped in the clock period that POP is asserted.
When the FIFO is not FULL and PUSH indicates that write data is present, data will be pushed into the write side of the dual-port RAM at the write address pointer while incrementing the pointer. When the write pointer catches up with the read pointer, the FULL flag is set and remains set until POP is asserted.
When the FIFO is not EMPTY and POP indicates that read data is requested, data will be popped from the read side of the dual-port RAM at the read address pointer while incrementing the pointer. When the read pointer catches up with the write pointer, the EMPTY flag is set and remains set until PUSH is asserted. The synchronous FIFO can be modified for asynchronous operation.
As the write-side and read-side state machine dependencies are purely combinatorial, the mean time between failures of the asynchronous FIFO is identical to the metastable characteristic of a single master-slave flip-flop. Occasional FULL and EMPTY conditions will assert and fall back according to the flip-flop metastable characteristics. The false assertions that occur due to binary rollover decode spikes can be reduced by using Grey-code counters. Even though the Grey-code sequence allows only single-bit transitions, there will still be occasional metastable events, but at the minimum rate.
In an asynchronous write-side state machine, when the FIFO is not FULL and PUSH indicates that write data is present, data will be pushed into the write side of the dual-port RAM at the write address pointer while incrementing the pointer. When the write pointer catches up with the read pointer, the FULL flag is set and remains set as long as the read and write address are equal.
In the asynchronous read-side state machine, when the FIFO is not EMPTY and POP indicates that read data is requested, data will be popped from the read side of the dual-port RAM at the read address pointer while incrementing the pointer.
When the read pointer catches up with the write pointer, the EMPTY flag is set and remains set as long as the read and write addresses are equal.
