Built on a 0.25-micron, four-metal SRAM process, the 102-mm2 chip is the product of four years of research at NEC Research Laboratories. Though the company said the chip is yet to be fully tested, preliminary results show a significant speed gain over microprocessor-based software for processing at least one representative algorithm.

The work represents not only a watershed for the nascent reconfigurable-computing industry, but also an attempt at a leapfrog maneuver by NEC. Like other Japanese semiconductor vendors, the Tokyo company has sat out the entire programmable-logic market to date.

"From the beginning, we didn't focus on FPGAs," said Masato Motomura, principal researcher for NEC's System ULSI Research Laboratory (Kanagawa, Japan). "That work is now done. Instead we're working on reconfigurable computing, and whether we productize this or not depends on whether this type of paradigm is possible."

Reconfigurable computing has been an active area of development in the United States for some time, and a few shipping products are based on the technique. But to date, development has been done with existing SRAM-based FPGAs. This has imposed some limitations on the resulting systems. Designed for general logic implementation, FPGAs lack specific features of rapid reprogrammability as well as dedicated internal buses, and often have too little interconnect to ensure that even a small change in the programming can be accomplished without altering the chip's entire configuration.

NEC's dynamically reconfigurable logic engine (DRLE) addresses these issues. The architecture comprises a 4 x 12 array of logic blocks, each of which in turn consists of a 4 x 4 grouping of "unified cells." These cells-the basic units of reconfigurable hardware-are connected to global and local buses and to a repeater for the local bus.

The unified cell is divided into a memory region of eight cells and a column circuit with a crosspoint switch and a read circuit for logic. That scheme is similar to the four-input lookup table used in FPGAs, but is much more sophisticated. In particular, the unified cell is able to allocate its resources as either logic or interconnect, whichever is most needed at that point.

"The unified cell is a kind of lookup table to generate logic in an FPGA, but in this case it can also be used to generate memory and switch-mode functions," Motomura said. "In a sense, the unified cell can be used for logic and as an interconnect switch. Some circuits require a lot of logic but only a small amount of interconnect. With this, the cell can either be logic or a switch by changing the context."

By storing multiple contexts-each of which carries a particular device configuration-on-chip, NEC is able to slash the reconfiguration latency from the minutes it takes to reprogram a large SRAM FPGA to only 4.6 nanoseconds. On the prototype device, the area required to store the eight contexts saved is 35 percent greater than the area of an equivalent FPGA, but NEC claims the benefit is eight times more usable gates. And in the future, using DRAM instead of SRAM cells to save context, the company can potentially pack 256 contexts together instead of eight, Motomura said.

One disadvantage, however, is power consumption: The chip demands power not only when performing logic operations, but when changing contexts. The experimental chip eats more than 100 mW for every 10 mega-reconfigurations per second.

The chip is still in the early evaluation stage, but initial performance tests hold promise. NEC compared the DRLE running at 33 MHz at 450 mW against a 200-MHz microprocessor dissipating 150 mW. Each device was required to make a 1-bit change in a DES encryption algorithm. The MPU took 906 cycles for a total of 4,530 ns, while the DRLE chip was able to process the bit in one 30-ns cycle, requiring not only far less time but far less total energy.

Software limitation
"MPUs are designed for 32- or 64-bit words. If you have to handle 1 bit, it's a tedious operation," Motomura said. "It takes three to four instructions to shift to the desired position. An MPU has to do this 64 times for each bit, and changing one bit takes several iterations. This is the inherent limitation of software."

Motomura said he does not see reconfigurable logic replacing MPUs, but rather working alongside them where it makes sense. The most promising application is network management, a space where Motomura envisions reconfigurable logic devices, MPUs and digital signal processors working alongside one another.

"The optimum architecture is a couple of MPUs, DSP plus this type of accelerator," he said. "The MPU does management tasks while this [reconfigurable part] does the processing of small data elements. Those include encryption, protocol handling, addressing functions and packet forwarding."

NEC has also started development of software tools for the device. "NEC has a good hardware compiler called Cyber, used for automatically generating a net-list for ASICs or FPGAs, and that can be easily used for this purpose," Motomura said.

Other voices
While the DRLE represents the most recent foray into reconfigurable computing by a semiconductor company, it is by no means the only one. Atmel Corp. currently supplies the CacheLogic family of FPGAs, based on an architecture pioneered by now-defunct Concurrent Logic. These devices store one set of configuration bits in a buffer while using a second set. This allows them to be reconfigured on the fly.

Motomura also made reference to a paper presented in 1997 by Xilinx Inc. researcher Steve Trimberger on the use of a multicontext architecture. Xilinx in fact produced engineering quantities of the device, a very large prototype FPGA that stored several control bits for each programmable pass gate. By changing a control signal, the user could select which control bit was used, thus switching among several configurations, much as the NEC device does.

Xilinx has no plans to turn that device into a product, but has incorporated lessons learned from that research into its new Virtex family. A company source confirmed that the Virtex hardware includes, along with much richer interconnect resources, support for rapid, on-the-fly partial reconfiguration. The feature has not been described to customers because of still-unresolved software issues, the source said, but it is operational in the parts.

Research into the problems of creating an FPGA for reconfigurable architectures is also ramping up in universities. The FPGA-99 conference in Monterey, Calif., next week will include papers on a number of issues vital to reconfigurable computing, including how to balance utilization efficiency and logic optimization-the most valuable factors in conventional FPGA use-against programming time, which is looming large in reconfigurable applications.

Papers will also explore several new architectures from the University of California at Berkeley, Brigham Young University and the University of Toronto, and will look into data-driven reconfiguration techniques, programming tools and other vital issues. — Additional reporting by Ron Wilson.