SAN FRANCISCO, Calif. — With two ISSCC papers on Silicon-on Insulator (SOI) PowerPC chips, IBM Microelectronics has barely scratched the surface of SOI's promise, according to the company's engineers. The future of the technology is open-ended, beginning with the obvious promises of improved power and performance, but including more subtle advantages and reaching to new, as yet unimagined structures in silicon.

IBM engineers reported on the development of two different PowerPC implementations — one commercial CPU, and one for IBM's own AS/400 division. While both designs reported gains in power consumption and speed over comparable bulk CMOS designs, both were relatively simple extensions of existing circuitry and methodology. Basically, circuits from existing CMOS CPUs were picked up, plopped down on an SOI process, and only modified if they broke.

But an exciting future awaits in the next phase of SOI development. "We have been doing first-generation SOI designs, using basically CMOS design work moved to new libraries,'' explained IBM engineer/scientist Steven Voldman. "Now we are entering the second generation, where we move from conventional MOSFETs to dynamic-threshold MOSFET structures.''

Research at IBM and from other labs indicates that big gains in device performance are possible by dynamically controlling the body voltage — and hence the threshold voltage — of transistors in an SOI device. This change by itself will result in library elements with significantly better performance than would be possible even with conventional fixed-threshold MOSFETs on an SOI wafer.

But that will be only the beginning of the evolution, according to the IBM engineers. More advantages are to be gleaned by changing circuit designs as well as transistors.

"For instance,'' said researcher Dennis Cox, "there are situations with SOI where it is very advantageous to use pass-gate logic instead of conventional logic. In SOI, stacking is good, where in bulk CMOS it's a problem. And there are times when a very large programmable logic array (PLA) — much larger than could be done easily in bulk CMOS — makes a lot of sense.

As SOI opens up new possibilities, it also seems to remove old problems. It is well known that SOI reduces parasitic capacitances that inhibit speed in bulk CMOS. What may be less obvious is that it also eliminates parasitic diodes and transistors that are the plague of bulk CMOS device modelers' lives. In this way, the move from bulk CMOS to SOI may have the same happy effect on device modeling, isolation and packing limitations that the move to copper has had on interconnect modeling. It just makes life simpler.

In the near future, customers are likely to find the introduction of SOI to be almost transparent. The differences between SOI and bulk CMOS will be hidden inside ASIC libraries, with the ASIC vendor stepping in to do some custom work when something really needs to be different above the circuit level. But as SOI matures, the IBMers predicted, changes will start to surface even for logic designers. New tools will emerge, new techniques will be preferred, and, eventually, some rather revolutionary possibilities will exist.

Changes that are in process but not yet on the public road map are exciting. IBM is reportedly internally working on SOI analog circuitry that takes full advantage of the availability of variable-threshold transistors. In fact, some of those techniques were used in the design of the SRAM cache for the PowerPC chips. In addition, the isolation between circuits that comes more or less for free in SOI means the elimination of guard rings, easier handling of RF on a mixed-signal die, and, startlingly, much better techniques for dealing with electrostatic discharge resistance.

Further in the future, IBM is intent on moving its trench-capacitor DRAM technology to SOI. "We are not ready to talk about details yet,'' said IBM vice president and fellow Bijan Davari, "but stay tuned. I can only say that the results so far have surprised us.''

Even further out — but already in the laboratory — is a more revolutionary change. In theory, it should be possible to create a multistory IC by building an SOI device, putting a thick layer of oxide over it, and then fabricating another layer of active circuitry on the new oxide. This process could be continued, in theory, to create almost arbitrarily large stacks of circuitry.

The IBM designers acknowledged that, assuming that you are using partially depleted rather than fully depleted SOI, the circuitry is relatively insensitive to small deviations from a perfectly flat oxide surface. And they admitted that a multistory device is more than just theory. "Such devices have been fabricated in the lab,'' one engineer confirmed.