A system creates an EMI spike that matches its clock frequency. As processor speeds increase, the peaks can become severe enough to violate Federal Communications Commission regulations. Spread-spectrum clocking speeds up and slows down the clock within a few percent of its target frequency, thus flattening out the EMI peak by spreading it across a range of frequencies.

Hung-Sung Li, a principal engineer at graphics-accelerator company NeoMagic Corp. (Santa Clara, Calif.), presented a dual-loop spread-spectrum concept. Li's paper described a clock generator, directed primarily at laptop-computer systems, that uses a phase-locked loop coupled with a "slave" modulation-voltage-locked loop (MVLL).

The PLL generates a regular clock wave. The MVLL generates a triangular wave that, after being scaled down accordingly, is added directly to the PLL wave, creating a clock whose frequency shortens and lengthens at regular intervals. According to Li, the triangular wave has proven better than a sinusoidal wave at flattening frequency peaks.

Li further noted that an even more effective wave, which inflicts rapid variations on the clock frequency, has been patented by K.B. Hardin, who in 1994 presented a seminal research paper on spread-spectrum technology.

It's vital for the MVLL to alter clock frequency in a regular pattern, because otherwise it might interfere with the PLL's regular operations. Li noted that it's possible for the MVLL's modulation to affect graphics: A vertical line could be drawn with a "wobble" that matches the speeding and slowing of the clock.

The MVLL itself produces reliable output even under wavering supply voltages, Li said. NeoMagic's tests showed that as supply voltage varied between 3 and 3.6 V, the MVLL output remained within 5 percent of its target value.

Testing the part on a 1,024 x 768 display with a 65-MHz pixel clock, NeoMagic was able to reduce peak EMI by 5.9 dB by altering the clock frequency 1 percent. A 5 percent variation reduced peak EMI by 11.2 dB and cut higher-frequency EMI by as much as 16 dB, Li said.

NeoMagic built the dual-loop spread-spectrum clock using a 0.30-micron, 64-Mbyte dynamic-RAM process.

Moon's phase approach

Using a delay-locked loop (DLL) instead of a PLL, Moon's circuit changed the phase of the clock between 0° and -180°, gradually switching between the two using a 16-cycle speed-up or slowdown ramp. The circuit uses a pseudorandom number sequence to decide when to shift the clock's phase.

The method was developed in order to avoid accumulated phase error, a condition that occurs in PLL-based clocks. Unchecked, the error can accumulate to cover tens of clock cycles, Moon said.

Tests have shown the chip can reduce peak EMI by 13 dB when the input clock is 164 MHz. Moon's chip has been fabbed in a 0.35-micron, three-metal-layer CMOS process and consumes 45 mW operating at 3.0 V.