SANTA, CLARA, Calif. — Tensilica Inc., which announced this Monday (2/15) a 32-bit configurable processor architecture and tool kit for specialized applications, has leveraged concepts from RISC and VLIW. Xtensa, a 32-bit, low-power instruction set targeting mobile applications, achieves up to 250-MHz performance in quarter-micron CMOS.

Chief executive officer Chris Rowen, who worked on the original MIPS instruction set, said the idea behind the architecture was to provide a way to optimize the processor core for a variety of applications, such as digital cameras, office-automation products, wireless communications devices and consumer-electronic products.

"Designers are being forced to design around a processor instead of architecting a system solution with optimal processing capability," he said.

Current processor cores are based on a technology that's nearly a human generation old and was designed usually without embedded applications in mind. The MIPS instruction set, for example, targeted workstations first and happened to extend well to embedded applications after a time. Rowen also points out that the contemporary cores-based design locks in a designer to a process, which can raise the cost of silicon.

"We need to get around the rigidity of this process," he said.

The Tensilica approach avoids that and gives designers a flexibility in an applications area that they really don't have with an off-the-shelf core, one that they may be able to optimize but only for limited features like cache sizes.

At the core of the approach is the Xtensa instruction set, developed by Rowen and others with VLIW and RISC concepts as a backdrop. The ISA is designed with high code density in mind and includes more than 70 base commands, both 16- and 24-bit versions. The architecture allows considerable flexibility in powering down various blocks and the RTL file can be ported to low-voltage libraries following synthesis. The architecture claims better bit manipulation, including funnel shift, bit test and branch instructions, and support for speculation and instruction-level parallelism.

The core takes up just 25,000 gates of logic in quarter-micron CMOS and can be built in less than eight hours, Rowen said. He also claimed the code is 10 percent smaller than ARM Thumb.

Tensilica's offerings also include a development kit based on industry-standard GNU tools, including a compiler, linker and debugger. A browser-like interface in Tensilica's Xtensa processor generator (XPG) allows easy configuration management, from additional core functionality to instruction-set extensions.What XPG spits out is a foundry-independent RTL file. Designers can pick a manufacturer's cell library and synthesize the design using Ambit's BuildGates tool or Synopsys' DesignCompiler.

Licensing fees for the processor and tools start at $350,000 and the company also charges royalties based on the number of units manufactured.

The company has lured several notables from the semiconductor and EDA worlds, including former Synopsys chairman Harvey Jones as Tensilica's chairman, Intel veteran Beatrice Fu as vice president of engineering and MIPS and SGI veteran and multiple patent holder Earl Killian as chief architect.

While the company has landed $13 million in venture capital from outfits including Oak Investment Partners, it remains to be seen whether the business model will catch on. The company has landed customers at Zilog and startup Silicon Spice, run by onetime Pentium project leader Vinod Dham, but Tensilica will have to displace a lot of entrenched designers using relatively inexpensive cores and off-the-shelf tools to make a go of it.