SAN FRANCISCO — While the keynote address by Broadcom founder Henry Samueli mapped some exciting achievements and prospects for building high bandwidth communications circuits, opening-day presenters at this week's International Solid States Circuits Conference (ISSCC) were more modulated in their assessments of the ability to build a single-chip cell phone.

Nevertheless, presenters in the session on "RF and Analog Techniques" explored devices and processes that could potentially unseat GaAs transistors in cell-phone transceivers. The candidates included silicon germanium (SiGe), BiCMOS and CMOS — and micromechanical machines for the passive components. While the experimental achievements in each of these technologies were promising, there was little to indicate that this would promote large-scale integration with baseband processors anytime soon.

The issue is significant since the single-chip cell phone will depend on the ability to integrate the RF front end — transmitter power amplifier (PA) and low-noise amplifier (LNA) receiver components currently fabricated in GaAs — onto the same CMOS substrate with microprocessor and DSP baseband components. While GaAs FETs are inexpensive and highly efficient at GHz frequencies and cellular handset power levels, they require a split voltage power supply (i.e., a negative bias voltage) — a nuisance to cell-phone manufacturers. More significantly, GaAs offers a limited ability to integrate. Thus, cell-phone makers are looking for RF ICs (PAs, LNAs, mixer-oscillator components) that could be readily integrated with the CMOS baseband processors.

In this environment, both IBM and Temic are promoting SiGe. Seshadri Subbanna, who manages BiCMOS technology research at IBM Microelectronics (Hopewell Junction, N.Y.), described some of the devices his team had built using high-frequency SiGe as the NPN heterojunction bipolar transistor implanted on a CMOS substrate. The devices include ECL ring oscillators, 4-bit D/A converters and A/D converters with 8-GHz sampling rates, frequency dividers and active filters. These devices could be integrated with DSP and CPU cores constructed in CMOS, Subbanna believes, though no practical methodology now exists combining the bipolar mixed-signal circuits with the digital CMOS cores. A practical consideration, Subbanna said, is making SiGe scale with CMOS coping over time and integrating copper metallization.

IBM is actually designing SiGe devices meant to be competitive with the GaAs FETs currently used in cell-phone front ends. These include a 1,900-MHz low-noise transistor and a 1,900-MHz Code Division Multiple Access (CDMA) driver amp. The low-noise transistor has 12-dB gain and a 1.2-dB noise figure. The multistage CDMA power amp also has 12-dB gain, but pumps out 10-dBm of power with 65 percent efficiency. Like GaAs FETs, the SiGe devices have fTs on the order of 40 GHz. Unlike GaAs, which requires a negative bias generator, the SiGe devices operate from single supply voltages. The 1,900-MHz transistor consumes 5.5 mA from a 3-V supply; the driver amp takes 20 mA.

In their first attempts to integrate SiGe and CMOS, said Subbanna, the company is working on a BiCMOS frequency synthesizer.

Temic Semiconductor GmbH (Heilbronn, Germany) built a complete DEC transceiver chip set using SiGe. Matthias Bopp, who heads Temic's wireless communications department, said that the transceiver was made up of two chips: an RF front end with PA and LNA in SiGe, and a DECT transmitter-receiver (including electronic tuner, demodulator, mixer and baseband filters) in bipolar technology.

The on-chip synthesizer and voltage-controlled oscillator operates over a 3.6-GHz tuning range. Its tuning slope is 60 to 90 MHz per volt. The advantage of the bipolar process, Bopp pointed out, is its low noise. The phase noise of the transceiver was -90 dB, and its third order intercept (IP3, a measure of its selectivity in a crowded signal environment) was +8 dBm.

But it was the SiGe RF front end which was of most interest to front-end integrationists. Bopp said the process supports spiral inductors, nitride capacitors and polysilicon resistors (up to 50 passives are in the DECT RF front end), as well as 50-ohm matching components.

Apart from BiCMOS, there is a great deal of speculation and experimentation with CMOS as a potential RF process. Five papers in the ISSCC session on "RF and Analog Techniques" explored the use of CMOS in RF devices. For example, Bendik Kleveland, a PhD candidate at Stanford University (Palo Alto, Calif.) described a 90-mW distributed amplifier he built in CMOS. The part has a unity gain bandwidth of 13 GHz.

Brian Ballwebber, a graduate student at Oregon State University (Corvallis) described the fully integrated 0.6-micron CMOS RF amplifier he put together with the help of Ravi Gupta of Maxim Integrated Products (Sunnyvale, Calif.). The amplifier puts out 85 mW at 900 MHz with a 55 percent drain efficiency at 3 V.

But the most attention-getting paper of the entire session was Klaas Bult's analysis of the analog broadband circuits in pure digital CMOS. Bult is director of Analog and RF Microelectronics Technology at Broadcom (Irvine, Calif.). And his paper drew standing-room-only crowds (many hundreds of engineers in addition to the 1,000 already seated) into the analog session room.

Voltage scaling is the major problem for data converters built in digital CMOS. You can build a good 10-bit A/D converter in 0.5-micron CMOS — one that runs on 2.5 V and samples at 100-MHz rates, he told the crowd. But it will not scale, he insisted. A reduction of the CMOS geometries will reduce the voltage margins required to prevent the CMOS FETs from going into saturation. A lower supply voltage is a problem since VD,Sat needs to be large, he said. Otherwise, the speed and accuracy of the circuit is degraded.

The noise, crosstalk and over-all power dissipation are also increased at lower voltages, and device pair matching becomes more difficult, Bult said. Analog circuits constructed in 0.35-micron CMOS, using a 3.3-V supply, may not have a problem, since VD,Sat is still around 350 mV. Circuits at 0.25 microns with 2.5-V supplies may not have a problem. But, at 0.18 microns and 1.7 V, "all circuits get into trouble," Bult said. You don't get the performance you need with a VD,Sat of 150 mV.

The solution may be to use thicker oxides to protect the transistors, and lower input voltage swings. "Look for architectures that decompose speed and accuracy," he advised.

After Bult's talk, one of the engineers standing in the back of hall — Jim Quarfoot, an amplifier designer and senior member of the technical staff at Texas Instruments (Dallas) told EE Times, "The digital guys assume this integration is simple and easy. It's about time somebody talked about the problems of analog design."