MONTEREY, Calif. — A panel at FPGA'99 here Monday (Feb. 22) peered into the future of FPGAs in the era of system-level ICs and saw deep shadows. While FPGA-vendor panel members touted the ability of huge new FPGAs to easily absorb large pieces of intellectual property (IP), or for hard IP macros to be integrated onto FPGA dice, panelists from the research and user communities saw things very differently.

In opposition to the notion that you can simply put an entire system-level design into an FPGA, University of Washington professor Carl Ebeling warned, "If all you have is a hammer, everything looks like a nail. But if we keep thinking that everything looks like it has an FPGA solution, we could get screwed."

Beyond the initial levity, Ebeling warned that for many applications, it is simply not good enough for an FPGA to do tomorrow what an ASIC can do today. "The gaps in power consumption and performance between FPGAs and ASICs aren't narrowing, they are growing wider," he said. "And those gaps are pushing more and more high-end applications not toward FPGAs, but toward ASICs."

Admitting that not everything can be done well in an FPGA, University of California Los Angeles professor Jason Cong said even adding some diffused hard cores to a chip doesn't solve the problems. Cong, whose influential work produced some of the first tools that could systematically map logic into the SRAM blocks on Altera Corp.'s Flex devices, warned that "the devil is in the software."

"There are very substantial problems in creating design software for devices that include both FPGA and hard blocks," Cong said. "Among them, it is quite difficult to automatically partition an algorithm among heterogeneous resources, even such common resources as programmable logic and SRAM. If you can do the partitioning, it is difficult to optimize the implementation of parts of the algorithm on each kind of resource. And if you solve that problem, there are still very hard problems involved in run-time communication between different kinds of blocks, scheduling and the like."

But if the arguments against incorporating either soft or hard IP into FPGAs were strong, the most sobering statements of the night came from a customer — a very influential customer.

"We are a major consumer of FPGAs," said Bill Harris of Cisco Systems Inc. And Harris' data showed he was being modest. Cisco claims to be currently the largest single user of programmable logic, shipping over one million PLDs of various sorts per month.

Once he had the audience's attention, Harris lowered the boom. "Despite that, I have to say that for large systems our trend is to ASICs, not to programmable-logic devices. On the systems that make up our platforms, we will spin an ASIC rather than use an FPGA."

Harris explained that a major phase was over in the halcyon relationship between the networking industry and the FPGA business. "In the beginning, it was a small Cisco competing against other small companies. Time-to-market was everything, and cost wasn't an issue. If we could get the latest speed grade of an FPGA, we'd throw it in just so we could start shipping."

But times are very different now in the industry, Harris said. "Now, we have established market share and established platforms. Customers aren't going to pull out our gear just because it takes a while for us to support a new feature. But there is intense price competition. We have the luxury of longer development times, but not the luxury of naming our own prices."

These factors, Harris said, were gradually weaning Cisco from use of programmable logic in complex or high-volume applications. This, if it proves generally true, could be an enormous challenge to the growth of an FPGA industry that has been feasting at the table of the networking and communications companies for several years.

But Harris wasn't through spoiling the evening for the FPGA vendors. "We have the resources and the tools now to do very high-performance, multi-million gate designs on single chips. One design we have in progress is approaching 20 million gates. FPGAs have neither the speed nor the density to approach this level.

"When we need field programmability, what we would prefer is not to have a huge programmable device, or even a programmable device with a huge piece of hardware set down beside it. We would prefer to have an FPGA core to drop into our ASIC. We typically need small amounts of reconfigurable logic beside the fixed hardware.

"Unfortunately, that doesn't seem to be the way the industry is moving," Harris said. "I think first we will see FPGA vendors try to provide IP on their devices. But that's not what we'd like. If we could get an FPGA core for use in our ASICs today, we would be doing that already."

The sum of the university and industry inputs from this very small but undeniably influential sample suggested bad news for the FPGA business. The strongest high-volume customers for FPGAs appear to be changing their buying habits. Increasingly, they are using ASICs instead of FPGAs. And when they need programmable logic, they intend to get it, if not from their ASIC vendor, at least as third-party IP, not as silicon. If this foreshadowing becomes a trend, it could force a major shift in business models for the largest programmable-logic vendors.