Monterey is backed by over $16 million in venture funding, and its founders and technical contributors have established track records in EDA and IC design. The company is planning an April introduction for its product, and is promising a single, integrated tool suite that performs all functions needed to take a gate-level net-list to a fully verified GDSII layout file.

Company executives include James Koford, president and chief executive officer, who helped develop the first engineering workstations at IBM and the first commercialized gate arrays at LSI Logic; Robert Blair, executive vice president of business development, a veteran of LSI Logic and Fairchild Semiconductor; and Jacques Benkoski, executive vice president of marketing and sales, who formerly managed the European subsidiary of Synposys' Epic division.

Technical input
Technical contributors include Lawrence Pileggi, chief technical officer, professor of electrical engineering at Carnegie Mellon; Sharad Malik, associate professor of electrical engineering at Princeton; and Majid Sarrafzadeh, professor of electrical engineering at Northwestern University.

"Physical-design technology in place today uses algorithms that were probably developed 10 years ago," said Koford. "Current products are handcuffed by a lot of legacy code. We feel there's an opportunity to start with a clean sheet of paper and a new approach, and that's what Monterey is all about."

The company's mission, said Koford, is to provide an integrated IC layout solution for multi-million-gate chips that delivers a tenfold reduction in "design closure time," removes uncertainty, and makes chips more predictable.

Monterey, however, is revealing very little about what its solution will include. "It will be a single product that offers all capabilities needed to take you from net-list to GDSII," said Benkoski. Asked if it will include placement, routing, parasitic extraction and analysis, he replied, "All those will be there in one form or another, but not necessarily in a form known today."

Benkoski acknowledged, however, that customers will probably use third-party physical verification tools to check the results of the Monterey product.

To make its mark in physical design, Monterey must not only compete with two well-entrenched market leaders in this area — Cadence and Avant! — but must also argue against the new design flow advocated by Synopsys, which has just announced Chip Architect, a product that includes full placement and global routing. In Synopsys' view, cell-level routing is the only job left for the back end — and Monterey clearly plans to offer more than that.

"It's fine if they go further down and do some placement, but for somebody to claim they can take a placement and just do routing is too optimistic," said Benkoski. "We think we would redo that placement."

Since Monterey does not intend to offer presynthesis design planning, it must also counter arguments from Cadence and Avant! that the vendor who provides design planning must also supply the final placement and routing tools. And it is not yet known how Monterey's product will link up with logical design tools such as synthesis.

John Barr, analyst at Needman and Co., commented that Monterey has a "very experienced and capable team." He also said the company has outlined an approach that appears to fit in with the existing design infrastructure. However, Barr also noted, Monterey has not yet shared any technical details about its product.