Introduced in 1998 to run under Unix, A/RT Builder now stands at version 1.5 and can be used on an NT workstation to automatically translate C-language algorithms, including fixed-point algorithms, into Verilog or VHDL descriptions.

The HDL output from A/RT Builder can be synthesized into FPGA, PLD or ASIC hardware architectures using third-party synthesis tools. The output has been optimized for synthesis using Design Compiler from Synopsys and Exemplar's Leonardo Spectrum synthesis tool.

Frontier has also ported the companion tool, A/RT Library, to run under the Windows 95, 98 and NT operating systems. A/RT Library provides a set of C++ data classes and operators that encapsulate the characteristics of fixed-point arithmetic accounting for quantization and overflow effects. In addition, the semantics of A/RT Library have been proposed to the Virtual Socket Interface Alliance for adoption as a standard.

"System designers typically work in the C-language to develop and simulate their designs," said Herman Beke, chief executive officer of Frontier. Once the design works, it must be carefully rewritten in an HDL — a time-consuming, cumbersome process, Beke said. "Futhermore, HDL simulators are at least an order of magnitude slower than native C execution and they do not have the system-level application libraries, such as CDMA, GSM and RF or radar, that are required to get a reliable design."

An added feature of A/RT Builder 1.5 is that it can inhibit the generation of latches that may be inferred by an HDL synthesis tool when a non-static variable gets a value assigned in specific branches of an "if" or "switch" statement.

The A/RT Builder and A/RT Library combination is priced at $20,000.