DCDL will come into public view this week as Open Verilog International announces that the Design Constraints Working Group (DC-WG) has decided to accept the Cadence constraints as its starting point. The DC-WG-a joint effort between Open Verilog International and the Virtual Socket Interface Alliance-is working closely with the System-Level Design Language (SLDL) committee that recently joined VHDL International.

The DCDL effort is significant because the entire chip-design flow has become constraint-driven, and verification and physical design tools should ideally work from the same constraints as synthesis tools. With the SLDL connection, the DCDL effort is also aiming at system-level constraints that can be propagated throughout the design cycle.

"What it means for designers is that they're going to gain an interoperable way to describe more complex design parameters, and get their products analyzed and synthesized faster," said Steve Schulz, president of VHDL International and senior member of the technical staff at Texas Instruments Inc.

DCDL is a "multiyear" standards activity that will initially focus on timing constraints during the implementation phase, said Mark Hahn, DC-WG chairman and senior architect at Cadence. Hahn also serves as vice chairman of the Virtual Socket Interface (VSI) Implementation/Verification development working group, which is very likely to adopt DCDL as a VSI standard, he said.

In addition to synthesis tools, Hahn said, the initial DCDL activity will consider timing-driven placement and routing, floor planning, physical optimization and estimation. "We're starting with register-transfer-level design constraints and expect to add more system-level constraints over time," he said. "The joint working group is ensuring that the syntax of DCDL is compatible with the syntax of SLDL."

In addition to semantic consistency and portability across RTL tools, said Schulz, DCDL potentially provides consistency and portability across different levels of abstraction. The SLDL group is thus leveraging the DCDL activity as it develops system-level constraints in such areas as behavioral synthesis and hardware/software codesign.

Synopsys is monitoring but not actively participating in the DCDL effort, said Karen Bartleson, manager of interoperability at that company. "Synopsys sees much more value in using the de-facto standard that's out there now," she said, noting that Synopsys is licensing its synthesis constraints through its Tap-In program, and that Cadence is one of the licensees.

Synopsys did not offer its constraints directly to the DC-WG committee, but offered to license them to any EDA companies who serve on the committee, she said. Synopsys licenses the constraints for a fee or as a "swap" for another company's formats.

Hahn said the DC-WG group is starting with the Cadence constraints because it wants "an open industry standard that results from input from a variety of companies." He said the scope of the Synopsys constraints is more limited than what the DC-WG wants, with its interests in such areas as system-level design, power and signal integrity.

But Hahn could not deny that Ambit has a tiny market share compared with Synopsys. "We are trying to define DCDL to be as compatible as possible with the existing design environments out there," he said.

The existing Synopsys constraints cover such areas as timing, power and test, Bartleson noted. But she acknowledged there could be some value to DCDL several years out, if it defines constraints that are consistent with the SLDL. "It seems like a good evolution for the industry," she said.