Companies like Sapphire Design Automation and Silicon Perspective Corp. have recently released combined placement and optimization tools, but Dolphin is different: Monterey claims it handles everything from a synthesized net-list to a verified GDSII layout file. Dolphin includes detailed routing, RC extraction and final verification, although Monterey's founders acknowledge that early users will probably run a tool such as Dracula, Hercules or Calibre as a sanity check.

Monterey appears to have the expertise and funding to mount a serious challenge to EDA industry leaders. Along with fellow startups Sapphire, Silicon Perspective and Magma Design Automation — which is expected to release a product shortly — Monterey is claiming to usher in a new paradigm for the design of sub-0.25-micron, multimillion-gate chips.

"What we offer that's unique is that in our approach all the steps are performed simultaneously, as opposed to sequentially," said Jacques Benkoski, president of Monterey (Sunnyvale, Calif.). Monterey calls this simultaneous approach "Global Design Technology."

Monterey claims a significant technology breakthrough with its "fluid-block design," which it says can "soften" the block structure imposed by the logic hierarchy and combine blocks at the physical level to implement the desired logic functions. Yet even though it flattens hierarchy where possible, Dolphin, which supports 64-bit Unix and multiprocessing, hasn't yet hit a limit in design size, the company said.

Dolphin is aimed at a third-quarter 1999 general release. Monterey has so far declined to name any customers, although Benkoski said that "established market leaders" in various applications are looking at the tool. The company has offered no specific benchmarks showing reduced area or faster performance, although Benkoski said Dolphin is regularly producing both in customer designs.

The tool's main claim, however, is that it can reduce design time up to tenfold because it avoids iterations. Benkoski said that one pass of a Cadence or Avant! physical-design cycle is comparable to the amount of time Dolphin takes, but those existing tools, he said, may require 10 or more iterations.

"We are essentially claiming no iterations with the exception of certain special cases, which have to do with the constraints designers impose on us," he said.

User interaction minimal

Dolphin is largely a pushbutton tool, although there is support for incremental changes following engineering change orders. Although the tool outputs standard formats such as GDSII, Design Exchange Format (DEF), Standard Delay Format (SDF) and Standard Parasitic Format (SPF), bringing a third-party tool or utility into Dolphin may adversely affect its simultaneous-design capability.

The input into Dolphin includes a synthesized gate-level net-list, floor-plan data and constraints. The floor-plan data is not mandatory but can help with macrocell placement. Constraints are mostly timing constraints, which can be provided in Synopsys Design Compiler format. Dolphin can make an early call as to whether constraints can be met, but chip resizing won't be available in the initial version.

In addition to the GDSII file, output includes Spice data, a hierarchical Verilog net-list appropriate for formal verification, DEF, SDF and SPF.

Placement uses neither quadratic nor simulated annealing techniques, said chief technology officer Larry Pileggi, a professor of electrical engineering at Carnegie-Mellon University (Pittsburgh). "We have a placement algorithm that can work with various-sized objects, and also a very open cost function, so we can truly optimize wire-length congestion and timing," he said.

Dolphin may perform timing and logic optimization during any placement move. It also watches for such second-order effects as crosstalk, IR drop, noise and electromigration. Clock-tree building starts early and is refined throughout.

A static-timing analysis program runs at every step of physical design. Dolphin does not run a power analysis, though it helps construct the power grid and does power-and-ground routing. More elaborate power optimization may be added in later releases, Benkoski said.

The router uses a shape-based or gridless approach and can also snap to a grid where appropriate. Because Dolphin has already looked at wire congestion and problems such as crosstalk, the router has an excellent chance of coming to completion while meeting all user constraints, according to Pileggi.

Extraction starts early with precharacterized models. As the design progresses toward the back end, the models get progressively more detailed, culminating in a 3-D resistance-capacitance extraction on selected nets, Pileggi said.

Delay calculation, which Benkoski called "one of the jewels" of the approach, starts with approximate models and progresses to a full moment matching.

Available under Windows NT or Unix uniprocessors or shared-memory multiprocessors, Dolphin supports both 32- and 64-bit workstations. Pricing will start at $419,000.