The Architectural Synthesis Toolkit is an addition to the company's A/RT Builder tool, introduced at last year's DAC, that aids interactive synthesis and design exploration in the C domain prior to automatic translation into VHDL or Verilog. A/RT Builder and its associated A/RT Library translate C-language descriptions of floating-point algorithms into fixed-point VHDL or Verilog.

Frontier, the startup formed in 1997 by a management buyout of Mentor Graphics Corp.'s European Design Center here, also offers the Mistral behavioral synthesis tool, which produces synthesizable VHDL from a proprietary behavioral language.

Frontier claims that its architectural-synthesis extension can achieve die-size, performance or power-consumption improvements of 50 to 90 percent over conventional methods by allowing more extensive exploration and tuning of designs to system-level goals. The company also says the tool can halve design time compared with handwritten Verilog or VHDL at the register-transfer level.

Moreover, "Since the designer has more control, the synthesis process is very quick," said Herman Beke, chief executive officer of Frontier.

Indeed, Marc van Canneyt, vice president of business development, said that even for complex designs, compilation times are about 10 minutes.

"C is a natural for describing behavior,"said Van Canneyt. System designers perform algorithmic work and simulations in C as a matter of course, but van Canneyt said that until the introduction of A/RT Builder their final optimizations had to be reinterpreted and recoded in VHDL or Verilog, which was time-consuming and frequently a source of error.

"The Architectural Synthesis Toolkit gives system designers the opportunity to play with arithmetic-logic units, multipliers, ROM, RAM and so on, to get the clock frequency, power consumption and die area they want," he said.

Behavioral tools such as Mistral, Mentor Graphics' Monet and Behavioral Compiler from Synopsys Inc. "work in a black-box fashion," he said. "They come up with a solution, but what we've found with Mistral is that this limits the amount of exploration." Van Canneyt also pointed out that none of the previously established behavioral tools begin from C description.

The Architectural Synthesis Toolkit starts by compiling the algorithmic C code. A structure browser then highlights such features in the code as calls, loops and functions. The user selects resources from an extendable library that includes ALUs, adders, multipliers, ROM, RAM and application-specific units that can be defined in terms of behavior.

The software helps the engineer specify resources and assign specific operations in the code to specific resources. The Architectural Synthesis Toolkit can handle designs of a complexity of 100,000 mathematical operations or more, according to Frontier. "The biggest design we have done so far is 280,000 gates," said van Canneyt.

The software also performs scheduling — the ordering of operations in time. The scheduling can be based on various strategies, such as ASAP (as soon as possible), ALAP (as late as possible) or LIST, which is essentially an order derived from the order in which the code is written but modified by certain heuristic rules.

"ASAP tends to create faster operation, but requires more storage, while ALAP produces a slower schedule but uses less registers and is therefore a smaller design," said van Canneyt.

The tool also profiles activity in terms of computation cycles and histogramming routines so that the user can see in a particular setup which resources are oversubscribed or underused.

For power consumption it is difficult to have absolute numbers for functions, such as multipliers, whose detailed structures have yet to be determined at the VHDL level. "We have a library of blocks calibrated against a 0.35-micron CMOS implementation," said van Canneyt, "so these can be used to make judgments about relative power consumption."

While this exploration should arrive at an optimized and balanced data path, it is also necessary to derive the logic to control the data path.

"The designer can explore multiple architectures until the best result is achieved. Architectural synthesis extends designer creativity as well as designer productivity," said Beke. "And since the design can stay in C it is truly reusable."

Frontier's European design-services unit has been using an alpha version of the tool internally to synthesize blocks of C-language intellectual property into silicon implementations.

The tool kit will be available as an addition to A/RT Builder starting at $45,000. Frontier expects to start shipping it in July.