LavaLogic is the new name for TSI TelSys' reconfigurable computing division, which is developing the new software under a Pentagon contract. The 11-person unit plans to spin out as an independent company later this year, said Dick Bosenko, president and chief executive officer of LavaLogic (Columbia, Md.).

Bosenko, a former head of sales and marketing at InterHDL Inc., recently joined LavaLogic. Another recent recruit is vice president of marketing Bob Barker, who formerly served as vice president and general manager of Exemplar Logic.

While there has been some discussion about the potential of Java as a system-level language or high-level hardware description language (HDL), LavaLogic may be the first commercial EDA provider to bring that option into contemporary design systems. The company's Java-to-RTL compiler is an "architectural synthesis" tool that turns Java into synthesizable HDL code. Later this year, LavaLogic promises a tool that will take high-level Java descriptions down to gate-level net-lists, starting with FPGAs.

"Java appears to be the purest language to solve the productivity problems currently at hand," said Bosenko. He and other Java advocates claim the language can express high-level concepts with far less code than today's HDLs, yet offer more support for concurrency than C or C++.

Specifically, LavaLogic claims that the code required for a functional description in Java is typically one-tenth that required for Verilog. Java simulation models are 100 to 1,000 times faster, the company said. Moreover, Java is a widely supported, standard language for which many development tools are available.

LavaLogic first looked into C and C++ as high-level HDLs but found that was the wrong path to take, said Toby Bennett, LavaLogic vice president of engineering and founder of TSI TelSys. "We encountered a number of characteristics in those languages that would create pretty big inefficiencies or limit you to certain architecture types," he said.

Bennett cited C language pointers as an example. Those, he said, cause designers to infer memory and arithmetic resources they may not need and may also force designers into a sequential architecture because of an inability to resolve exact memory locations.

A classic problem with C and C++ is their inherent inability to express concurrency. In Java, Bennett noted, concurrency can be explicitly invoked with threads. But these aren't required, Bennett said, because LavaLogic's software can also detect concurrency using data-dependency analysis.

Bennett said the Java-to-Verilog RTL compiler uses "standard" Java with a minimum of libraries for I/O interfaces. Since the tool stays at the architectural level, technology-specific libraries are not needed.

One of the strongest advocates of Java-based EDA is Richard Newton, professor of electrical engineering and computer science at the University of California atBerkeley. Newton said that he's not affiliated with LavaLogic but said he has reviewed its technology and found it to be "reasonably pragmatic."

Newton said Java is well-suited for hardware descriptions because it has an encapsulated memory model and because it has threads that allow at least a "coarse-grained" level of concurrency. Companies using C for hardware design, he noted, have to extend or modify the language, effectively reverting to a special EDA language.

VHDL caution

LavaLogic's approach has "real potential," but more details are needed, said Steve Schulz, president of VHDL International and a leader of the system-level design language (SLDL) standardization effort. "I would prefer some more solid technical detail on how LavaLogic handles concurrency, including runtime-concurrent operation; how it represents the dimension of time and ordering of events and signals that flow in time; and other key concepts," he said.

The SLDL effort, Schulz said, sees Java as "a useful component in a larger fabric" but believes no single language syntax can meet all system-level design needs.

The as-yet-unnamed Java-to-Verilog RTL compiler will take in the "class" file that is produced by a Java compiler. Users will also add such global and regional constraints as latency, throughput and area.

The tool performs automatic scheduling of operations to clock cycles. Resource allocation, however, is mostly interactive at this point. Scheduling and resource allocation are two key components of behavioral synthesis tools.

Much of the tools' internal processing is based on what Lava-Logic calls a control data-flow graph (CDFG). "We have a model where control and data flow together," said Bennett.

The output of the compiler is synthesizable, RTL Verilog code. The compiler promises structured, pipelined logic that tends to be correct-by-design after functional simulation.

Later this year, when the Java-to-net-list product is available, LavaLogic will offer the kind of technology mapping found in RTL synthesis tools. But an intermediate step that produces RTL code is unlikely, Bennett said. FPGA libraries will come first, followed by ASIC support.

Pricing details are not yet available for the Java-to-Verilog RTL product, but Barker said it will range in the "tens of thousands of dollars." LavaLogic said the product will support Unix and Windows NT, and Linux is being considering.

Sun Microsystems is a beta site for the Java-to-Verilog RTL compiler.