HP is participating in the announcement — which a spokeswoman called "Intel's biggest disclosure since the X86 itself" — because it co-developed the IA-64 Instruction Set. Merced will be the first implementation of IA-64; it is scheduled to ship in the middle of next year.

In advance of the announcement, Intel released to the press embargoed copies of a manual detailing the IA-64 instruction set. However, EE Times separately obtained from independent sources that manual — entitled "IA-64 Application Instruction Set Guide," as well as another manual, "IA-64 Application Developer's Architecture Guide." Both guides have been circulating throughout the tightly knit community of IA-64 developers.

Interestingly, both books were briefly posted publicly on an Intel ftp site last week, but were taken down within a day of their initial appearance. One source close to the company said, only half jokingly, "that the inadvertent posting of the Merced manuals was a way to give the Open Source crowd a way to develop IA-64 code without signing a nondisclosure agreement."

Inside instructions

In technical terms, the manuals present the first public look at all the arcane permutations of the IA-64 instruction formats.

Intel has hyped Merced's floating-point performance, in a bid to beat back RISC competitors such as Alpha. In that vein, Merced is equipped with 128 floating-point registers. Of these, 96 are rotating (not stacked) and can be used to modulo-schedule loops compactly. IA-64 also has parallel floating-point instructions which can operate on two 32-bit single precision numbers.

Merced will be able to support programs contained mixed 32-bit and 64-bit code.

A set of 128 Application Registers are included to provide a view into program execution. The inclusion of performance-monitoring registers and the CPUID instruction are carried over from the previous architectures.

Each IA-64 instruction is categorized into one of six instruction types: A, I, M, F, B, or L + X. Three instructions are grouped together in the 128-bit instruction bundle for simultaneous execution.

On the multimedia front, "IA-64's multimedia instructions are semantically compatible with MMX and Streaming SIMD instruction technology," according to the manual. The latter are the opcodes informally dubbed MMX2, which appear in the Pentium III processor.

Software side

More than anything else, Intel's manuals provide further detail on the complexities of speculation and predication — the two VLIW-like techniques at the heart of IA-64. In practical terms, they are intended to remove unnecessary branches and cut down on memory latency. (According to Intel, Merced is not a VLIW architecture. It is an EPIC — explicitly parallel instruction computing — design. However, it does incorporate VLIW concepts, the company admits.)

To help software developers navigate such complexity, a third Intel document is circulating among the cognoscenti. It provides guidelines on where to go to obtain information on writing Merced applications for different operating systems.

For example, programmers interested in Windows NT-based apps are instructed to go to a Microsoft Web site to obtain more information.

Linux developers are directed to a separate site, while HP devotees are advised to visit a third site.

However, the complexity of the documentation on the instruction set makes it likely that developers will come to rely heavily on IA-64 compilers and performance-tuning tools such as Intel's VTune 3.0 to get their programmers up and running. In that regard, major vendors such as Intel and Microsoft are likely to be first out of the chute with IA-64 compilers, industry sources said. Indeed, Intel is already showing its tools to OEMs.

The sources added that the fact that systems OEMs do not yet have Merced samples has slowed system development somewhat. In response, Intel notes it has released an IA-64 simulator to aid in software and systems development.

Business angle

Intel discussed the features in Merced that make it "ideal for e-business and Internet computing as well as technical computing and scientific analysis."

That dovetails nicely with the strategy Intel launched last month at its financial analyst's meeting in New York. There, Gerry Parker, executive vice president of Intel's new business group, said Intel will embark on a new thrust to "become a leader in hosting, storage and delivery of Web content." The company will host applications and provide building blocks for the delivery of Web content and services.

A key component of this strategy will be to sell IA-64-equipped servers to outside customers as well as to situate them in Intel-owned data centers, where Intel will operate them for a fee, much like IBM does. Intel also plans a heavy push in the technical workstation arena to support apps such as EDA and scientific visualization.

For its part, HP has spent much of the last two years proselytizing for IA-64. Its high-end servers are also IA-64 ready (that is, Merced boards can be plugged into them when they're available), thus HP as an anxious as anyone else for IA-64 to be a business success.

Intel said it will post the manuals on its developers web site Wednesday.