The word configurable is getting a lot of play these days. It still retains its esoteric meaning for a group of researchers in reconfigurable computing. But the word has been appropriated by another movement in the industry: vendors who make somewhat customizable chips. This group has important subdivisions, based on where you do the customizing. That's a critical issue when chip architects try to use the flexibility of configurable logic to improve throughput in a compute- or data-intensive application.
One possibility, represented by configurable-CPU vendors ARC and Tensilica, is to add instructions to an existing-but not industry-standard-CPU. The approach has its advantages and disadvantages.
On the plus side, if you choose carefully, you can add instructions that are atomic elements for a whole class of algorithms. Thus you get the ability to accelerate all the algorithms in a category, without giving up the freedom that comes from having the algorithm basically implemented in software.
One of Tensilica's prospects has accelerated DES encryption by replacing extensive table-lookup operations with a set of instructions that calculate polynomial values. The instructions were chosen to solve the generic problem and still afford coders a lot of flexibility to adapt to particular situations.
But adding instructions to a CPU forces the high-speed data stream to flow through the memory structures of the CPU-the main memory, caches and register files-where it has to contend with instruction fetches, traffic from other tasks and context switches. Since the problem of accommodating streaming data in a load/store, cached processing environment is still under investigation in the industry, that isn't necessarily the best idea. In addition, it can be challenging to verify a CPU design in which the instruction set has been altered, no matter how carefully. Ask Intel.
Other architectures, such as the approach taken by CDMA startup Sirius Communications, put the configurability in dedicated datapaths, clear of the CPU and its sequential instruction formalisms. That can lead to substantially higher throughput. But it may require considerably more architectural sophistication on the part of the chip designer to configure a dedicated engine. And there would appear to be a greater risk that, faced with a changing environment, the engine would turn out to be more dedicated than configurable.
Both approaches will have their adherents, depending on how system designers rate the need for throughput against the need for design simplicity and flexibility.
RSS
RSS| 
Digital| 
Mobile
