Given this context, the sudden appearance of startups wielding plans to introduce new proces-sors may seem puzzling. Yet Cognigine (Fremont, Calif.), Tensilica Inc. (Santa Clara, Calif.), Triscend Corp. (Mountain View, Calif.) and Improv Systems Inc. (Beverly, Mass.), to name a few, are doing exactly that.

One rationale for launching a chip architecture is the appearance of new market opportunities in portable systems, coupled with the seemingly insatiable demand for network connectivity. Such applications demand a fresh blend of functions-real-time media stream operations rather than the more static central processing of isolated desktop or portable systems, which only need to keep up with the speed of human interface operations. In addition, consumer-oriented systems such as cell phones or wireless PDAs demand low development cost and power-efficient operation.

Improv's Cary Ussery and Diane Flynn believe that a new processor architecture needs to be backed by a fully integrated business plan in order to succeed in today's volatile markets.

It is difficult to find a simple feature that distinguishes the new architectures from previous generations of microprocessors, but one common theme seems to be flexibility of configuration. That particular quality addresses many of the demands of the market-fast development, low power consumption, real-time throughput-in a way that a fixed architecture cannot.

We will begin this week's Focus on configurable platforms with a design walk-through with several engineers who invented Improv Systems' configurable system-on-chip architecture, known as "Jazz." The walk-through details several stages of development, starting with a marketing perspective and followed by an overview of the architecture, the aspects of compiler design, a look at the user application-development environment and, finally, an application example for an HDTV system.

Later in the section, Tensilica's (Santa Clara) chief executive officer, Chris Rowen, offers his view on how application-specific configurability is remaking embedded design. And Chris Jay, vice president of engineering at Essex Technologies Inc. (San Jose), explains how a serial bus controller can be built using Triscend's (Mountain View, Calif.) E5 configurable processor.

Improv had its genesis with three design engineers, Cary Ussery, Oz Levia and Ray Ryan. The three, who were employed at Cadence Design Systems, were steeped in the problems of working with large-scale custom ASIC design, rather than microprocessor development. That circumstance, according to Ussery, who is now Improv's chief executive officer, gave the group an original view of processor architecture.

"We had quite a bit of experience in watching people put together ASIC designs," he recalled, "and generally, they tended to view those designs as unique." However, the experience of repeated ASIC design development helped Ussery and his colleagues identify important common elements. "Typically, they will design a high-performance data path and a state machine to control it, and then they put memory buffers between the various blocks," he explained.

Those basic design elements, the engineers realized, could be implemented in a deep-submicron IC using advanced techniques such as configurable logic and a very long instruction-word (VLIW) processor architecture.

"We can predefine the data path because logic is not as expensive as it used to be on die; put the control of the state machines into programmable control, which is an instruction set; and then place shared memories between them," Ussery said. "So you are still designing ASICs, but within a programmable architecture."

With that core concept in place, the Jazz architecture began to evolve into a new type of processor, complete with high-level software representations implemented as a Java class system. The linchpin became the compiler, which was charged with taking a high-level Java description of an algorithm and mapping it into the fine-grained, configurable ASIC model. The VLIW aspect of this is crucial in generating custom instruction sets for each new application, and configurability eased the task by assembling the instructions from a small set of basic, fine-grained operations.

While the resulting system might effectively address the engineering issues posed by new application areas and markets, the team early on realized that a strong business model would have to be integrated into the project. The three enlisted Diane Flynn, then a business manager at Hewlett-Packard Co.'s medical products division (Palo Alto, Calif.), to develop that model. Flynn and the three Cadence engineers became the founders of Improv Systems.

"While it may seem highly risky for a small startup to tackle such a comprehensive architecture, we viewed it as an opportunity to control the business risks involved in introducing a new product," Flynn explained. "Typically, startups will focus their expertise on a really good architecture or a new compiler, which then become point products in the value chain. With our comprehensive approach, we saw that we could control the whole value chain. So while it may seem like a big bite to take technologically, it actually helps us to manage the business risk."

Rather than go head to head with major semiconductor houses, the group enlisted them as customers, obtaining seed capital from several, as yet unnamed, semiconductor makers who will fab the chips and use them to make their ASIC customers more competitive in the volatile media-processing market. Ussery said that Improv's IC partners will be announced when first silicon arrives. The subsequent evolution of the company will provide some interesting data on a new architecture as well as a novel business approach to launching a novel processor.