While the processor, which can be licensed in synthesizable form from its developer, ARC Cores Ltd. (London), has attracted attention for its ability to incorporate extra instructions and hardware, companies are also using a sometimes-overlooked attribute: low gate count.

Israeli startup Brightcom Technologies Ltd. (Tel Aviv, Israel) uses four ARC cores as the basis of its first standard chip product, the BIC5004, also known as the IntelliMAC.

"The IntelliMAC is a general modem for packet-based transport," said Yuval Ben Ze'ev, president and chief executive officer. "We are using a layered Venturi-pipe model to create a fully programmable chip that will handle Layer 2 and upwards of any protocol."

Brightcom has divided a set of modem protocol algorithms into a generic pipeline and mapped that computation model to four ARC cores that operate on data serially, each core customized to the types of math required at each stage of the pipe. The chip will ship with software that implements the modem of choice on the pipelined IntelliMAC.

The first software routines will let the BIC5004 operate as the media-access controller (MAC) for a cable-modem built to the U.S.-driven Docsis standard.

Brightcom said the IntelliMAC architecture is applicable as the packet-flow processing engine for a variety of intelligent networking devices, including cable modems, digital set-top boxes, wireless LAN products, Internet Protocol (IP) telephony devices, IP switching devices, routers, packet engines and application-layer switches.

Ben Ze'ev said the advantage of the Venturi-pipeline model was that a series of new modem MACs could be generated in weeks since they were simply a matter of coding software to fit on a generic MAC platform.

Brightcom is now prototyping the BIC5004 design on a Xilinx FPGA. "It's a huge Xilinx FPGA costing $2,000 so it's only suitable for prototyping," said Ben Ze'ev. Brightcom is targeting the design at a 0.35-micron CMOS process from Fujitsu Microelectronics, which will act as a foundry supplier. "The ARC cores could run at 100-MHz or more in that process but we reckon 66-MHz will be adequate for the applications," he said.

Brightcom expects its first chips from Fujitsu in September and plans to ship the BIC5004 early in 2001.

A second example of multiple ARC processors on a single chip is being developed by Hyperchip Inc. (Montreal), another company moving toward wafer-scale integration to enhance the scalability of its parallel processing.

Two cores per cell

Richard Norman, founder, president and chief technology officer of Hyperchip, said the company is "developing our massively parallel processing approach to extreme performance routing with a single-chip architecture based on 16 cells per chip and the possibility of using multiple chips per system arranged in a variety of topological arrays. We have decided to put two ARC cores in each cell."

In addition to containing 32 ARC cores, each chip will offer up to 160 Gbits/second of I/O data bandwidth, Norman said, and the architecture will scale to offer petabit packet-routing capability in small air-cooled units.

Norman said the core's small size contributed to its selection. "If it wasn't lean, we couldn't have fitted 32 . . . on an ASIC," he said.

The chip is meant operate at a fundamental clock frequency of 125 MHz for Gigabit Ethernet systems, 133 MHz in a PCI bus and 155 MHz as the basis of a Sonet router. On-chip SRAM will likely operate at 1.5 times that, and the ARC cores could be double-clocked, Norman said.

While some FPGA-based systems may ship to early customers, Norman expects systems based on 0.25-micron CMOS ASICs, supplied either by NEC or IBM Microelectronics, to ship in the first half of 2000. Only two companies "can supply the type of package we require," he said.