"There's a lot of experimenting going on," said Forest Baskett, chief technology officer at Silicon Graphics Inc. and co-chairman of the Hot Chips program committee. "We'll be learning a lot over the next several years."

As Baskett implies, no single tack appears poised to achieve unchallenged market dominance. "There is a lot of uncertainty as to how to use the parallelism that advances in silicon are making possible," Baskett said. "It's clear that there is no one best way for all purposes."

Among the variations on this theme, Baskett pointed to "MP-on-chip, multithreading-on-chip and VLIW [very long instruction word]. There are some chips in the works that promise to have 15 processors on a single die."

Yet even mainstream microprocessor architectures aren't past their prime. "We haven't exhausted superscalar designs," noted Monica Lam, a professor at Stanford and Hot Chips program committee co-chair.

Software, too, is leaping forward. For example, instruction-set additions are emerging to facilitate processing of streaming multimedia data types and 3-D geometry calculations, from the likes of Intel Corp. and MIPS Technologies Inc., respectively.

When it comes to CPU architectures, one of the big debates now raging pits multiprocessing against multithreading (MT).

Software multithreading has long been supported in operating systems ranging from Unix to Windows. But it doesn't buy programmers much because of slow context-switching times the technique entails (the saving of registers and so on that must be performed when moving among threads).

Enter hardware support for MT. Often misunderstood, rarely implemented, hardware multithreading may be about to come into its own. Two of the main efforts to implement the technique thus far have been a project at the University of Washington and Stanford's Hydra CMP machine. The latter will be detailed at Hot Chips by project leader Lance Hammond.

In the commercial world, one of IBM's current-generation PowerPC chips, dubbed Northstar, does incorporate hardware support for multithreading. However, the initial incarnation of the upcoming, next-generation Power4 "Gigaprocessor" will not. Presumably, that's because IBM prefers to buzz out the new 0.18-micron copper process that will be used to fabricate Power4.

The initial incarnation of IBM's Power4 chip will garner attention at Hot Chips because it will incorporate on-chip MP, in the form of two processors on a single die. But it won't support hardware MT.

"There are two kinds of multithreading," said Joel Tendler, senior technology analyst in IBM's Server Group in Austin, Texas. "There's multithreading at the thread level, which is really under software control. The other kind, which is in hardware, makes it look like there are effectively two processors."

That's the case with the Northstar, where switching between threads occurs in a style akin to time-division-multiplexing.

Still, most architects look at the bounty provided by today's burgeoning transistor budgets and tend to opt first for MP-on-chip rather than hardware MT.

"People have shied away from hardware multithreading, because there are not many fine-grained [software] applications that take advantage of it," said Arvind, a computer science professor at the Massachusetts Institute of Technology. "In addition, there are competing solutions — like speculative execution [used in Intel's EPIC architecture] — which are more conventional."

Yet MT and MP need not be mutually exclusive. "We can use multithreading to solve some specific hardware problems, such as latency tolerance and synchronization rates," Arvind explained. Latency is shorthand for the speed of the microprocessor being much faster than the speed of memory access. "For example, a load instruction could take 100 to 200 cycles to give an answer back. I could do some useful work during that time — like go to another thread," he said. "That's how the idea of hardware multithreading came about."

Synchronization is similar. "Suppose I'm waiting for a flag to get set," Arvind said. "While I'm waiting for that, I can go do something else," such as process another thread.

In the real world, MT may need a boost from programmers to get up a head of steam. One promising point is the support from lightweight threads provided by the Java programming language.

"The question of should you introduce multithreading into a system is something of a question of how high-performance do you want to shoot for and what's the level of MP that the software can support," said IBM's Tendler. "Today, in many apps, the level of MP is limited by the software. There tends to be too much contention for similar data. The software needs to mature some more and improve on its ability to scale. I think we're seeing that happening."

Added Arvind, "The big [recent] change is the recognition that more than one program counter is needed" to get the most bang out of hardware-supported multithreading — that is, each thread would have its own program counter. "You will certainly see MP-on-chip in the next few years. Exactly what the programming model for it will be remains an open question. But multithreading could bring a lot of sanity to the game."

While on-chip MP vies to become the next big thing in general-purpose architectures, the latest trend bubbling up in more special-purpose chips is the software-centric CPU. Here, devices like the configurable, extensible CPU from Tensilica Inc., to be detailed at Hot Chips, are leading the charge. Such chips can offer a cost-effective way to address new applications via reprogramming, rather than designing a new, behemoth microprocessor architecture from scratch.

Hot Chips will also offer some insight into just how engineers will get such chips up and running for the task at hand. In a conference paper, VMware Inc. will detail its virtual machine monitor. "It's a way to debug software running on one operating system, while sitting on top of a native OS that's more stable," said a source close to the company.

Such "virtualized machines" may be the wave of the future, as mixing and matching between development platform and target platform becomes more common. That situation has prevailed for years in the embedded world, but it's now about to become a factor in the emerging category of Internet appliances.

VMware has apparently based its technology, in part, on an idea that's long been a favorite of theoreticians: Why be limited to a specific microprocessor architecture? Simply create silicon that supports a hardware abstraction layer and use software on top of that to mimic any architecture that's desired.

VMware is actually staking out more limited ground — namely Windows and Intel-related territory — but its scheme could be a harbinger of things to come.

Software tricks

Software is also rearing its head at Hot Chips in the form of instruction-set extensions. Intel will detail its now well-known Streaming SIMD Extensions (formerly called Katmai New Instructions), which boost the processing of multimedia streams and related data.

MIPS Technologies will disclose architectural extensions for 3-D geometry processing. A bevy of new instructions will facilitate processing of geometric cubes, which is considered the front end of the graphics problem. (Rendering will still have to be performed separately.) The instructions will appear in the company's upcoming 64-bit Ruby core, which will see first silicon in early 2000.

The extensions are aimed at embedded applications in set-top boxes, games and information appliances. "I don't know of any other architecture which has announced graphics extensions for the embedded market," said MIPS product manager Doug Maass. The instructions add less than half a square millimeter on a 0.25-micron-process chip to deliver 25 million polygons/second.