Processor IP is being used in the development of off-the-shelf network processors, and the IP providers are working with network processor companies to add communications-oriented features. From the user perspective, any off-the-shelf solution that is not fully programmable will suffer to some degree the same limitations of pre-network processor hardwired solutions: unused instructions and/or device resources, functions that are not really intended for the specific task at hand, and the general inability to alter the hardware design. Although many communications standards are well-established, there is often room for communications products to be differentiated in the actual details of implementation. Further, many more communications protocols are just coming into acceptance or are still in flux.

That environment has contributed to shorter product life cycles and increased upgrade frequency as manufacturers race to bring new communications products and upgrades to market. It has also fostered a desire by designers for more flexibility in their hardware solutions. In recognition of that need, many of the most recently announced network processors offer some degree of configurability, generally to support a set of communications protocols and a range of channels and services.

The maximum amount of design flexibility that can be achieved with an off-the-shelf product is with the use of programmable logic and processor IP. With that combination, system designers can create network processors to match their specific application needs while retaining the shorter development cycles associated with non-custom components.

The design strategy supports a wider variety of processing architectures and functionality than when using other off-the-shelf components. For example, a common approach to network processor design uses multiple processors to act on multiple packet streams, while an external set of functions performs such byte-level functions as cyclic redundancy checks (CRCs), hash table lookups or framing operations. Following that approach, some designers have built their network processors using familiar RISC-type cores. In support of the strategy, Lexra is working with communications companies to enhance its LX4180, a 32-bit processor core, to meet specific network processing needs.

The LX4180 is an R3000-class processor that lets users enhance the standard MIPS instruction set, which is used in networking applications by leading telecommunications companies. The LX4180 also lets users configure not only memory size but also memory organization, a capability designers have used in network security applications.

Since software is an important component of network processors, the availability of mature software development tools provided by the more than 60 MIPS third-party tool suppliers is a benefit to customers. "It's our intention to be the leading supplier of processor cores to network processor designers," said Pat Hayes, Lexra's chief technology officer, "and the ability to rapidly prototype designs using programmable logic has been absolutely critical for our design wins in this area."

Another approach involves using configurable-processor IP to include formerly external functions in the instruction set, and/or creating communications-specific instructions. Traditional microprocessors were designed for numeric or logical tasks: add with carry, branch if zero, toggle least significant bit, etc. Configurable instruction sets, like those offered by ARC Cores and Tensilica, allow designers to use communications-specific instructions, like "extract packet header, align it, log it and branch on destination IP address."

Custom instructions are an opportunity for developers to add value, perhaps even encompassing trade secrets or proprietary algorithms right in their instruction sets. The software for custom microprocessors can't be reverse-engineered, because the instructions are meaningless to outsiders. Also, the processor can be configured differently for different applications, or different models within a product line. Implemented in programmable logic, the processor itself-right down to the instruction set-can be upgraded in the field. Custom instructions can be simple, single-cycle operations like "test header field" or complex multi-cycle operations such as "manage packet queue" or "calculate CRC." Implementing elaborate, multicycle instructions in hardware slashes code size by replacing extensive software routines with a single instruction, and it also speeds network processing enormously.

Configurable-processor IP also allows the designer to create application-specific condition codes beyond zero, carry, negative and overflow flags. This way, branches can be made conditional on any imaginable condition. Every instruction can be conditional (i.e., predicated execution) for code that can "ADD if bad checksum," "shift left if queue is full" or "MOV if packet is from restricted domain." In many cases, register sets also need to be configurable. Different applications (router, xDSL modem, etc.) might call for different programmer models. Most programmers like to start with at least 32 registers, but even that quantity can be limiting if packets are assembled or stripped in registers.

For example, users of Tensilica's Xtensa can create up to 128-bit data types that directly load into the processor interface port. Xtensa allows communications designers to add an extra clock cycle to the instruction pipeline, which is especially useful in decoding large data packets in less time. "Configurable processors like Xtensa give system designers the flexibility to create and exploit new data types for high-speed packet communications," noted Mark Ross, director of hardware engineering for Cisco Systems. "Now, with the availability of configurable processors in programmable logic, the designer has a fast time-to-market option as well."

To a network designer, the most bandwidth at "wire speed" is the ultimate goal. The conventional approach to increasing bandwidth is to use fast, wide buses. With the availability of high-density programmable logic, the designer has the opportunity to take the highest-performance approach: eliminating the bus altogether. Buses-even on-chip buses-are a historical carryover from the days of printed-circuit board design. Instead of connecting the microprocessor to the network interfaces over a fast, wide bus, why not absorb these peripherals into the microprocessor design itself?

Bus-related problems (bus sharing and arbitration, timing protocols, bus-turnaround delays, write-after-read timing, bandwidth allocation and so on) are avoided altogether if there is no physical bus between the network processor and its peripherals or interfaces.

One ARC Cores customer is using ARC's configurable-bus structure to literally eliminate bus bottlenecks in its ultrahigh-speed (petabit, or 1,015 bits/second) 16-channel router design. Using programmable logic to prototype the design, the engineers were able to absorb each network channel accelerator into the ARC microprocessor, instead of clustering the channel interfaces onto a shared bus. Because each channel's registers are now part of the microprocessor's register set, transferring data from one network channel to another is just a trivial register-to-register MOV instruction. In normal situations, data travels freely from channel to channel. When network congestion is high, the ARC processor runs proprietary quality-of-service algorithms designed by the customer to prioritize and organize packets, routing the most critical information first.

"Configurable instructions, machine states and bus interfaces open up new vistas for network processor design," said Jim Turley, vice president of marketing for ARC. "It's amazing what you'll learn while implementing your custom processor within a PLD in an afternoon."

Network processor users often differentiate their product in software, using proprietary algorithms. With the integrative capabilities of programmable logic, they have more options to add value to their product. They can choose which functions stay in software, which functions become part the processor's instruction set (as in the previous example) and which functions get implemented in dedicated logic for the best performance. Systems integrators can add value in their specific area of expertise, and rely on the large offering of PLD-optimized intellectual property-including PCI master/target interfaces, Ethernet MACs, encoders and decoders, DES encryption-for the rest of the functions to ease the design burden.

Processor IP vendors such as ARC Cores, Lexra and Tensilica are working with both communications companies and programmable-logic vendors to provide features in their products that are optimal for network processing applications. The potent combination of programmable logic and processor IP provides an attractive balance of features for network processor designers: a high degree of flexibility together with the rapid development cycle of an off-the-shelf device. The result is a solution that meets the very difficult challenge of remaining nimble enough to keep up with a dynamic communications landscape.

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