The goal is to develop a synthesizable version of Motorola's 32-bit MCore processor based on the Theseus design approach by early 2001. The technical team at Theseus is developing a library of large-scale building blocks as synthesizable, reusable soft cores that can be used in system-on-chip (SoC) designs. Many of those designs will start out in programmable logic, which is prompting Theseus to seek a strategic relationship with at least one PLD vendor.

The Theseus approach is based on Null Convention Logic (NCL), pioneered by founder and chief technology officer Karl Fant. It creates "delay insensitive" circuits, which ease the timing issues that complicate the integration of multiple cores on system-on-chip designs.

An immediate advantage to data-driven logic is that the circuits kick in when work arrives to be done, which saves on power. Billy Edwards, a Motorola vice president of planning, issued a statement saying that Motorola has been tracking the technology for several years and sees immediate advantages for "solutions that require less power and create lower noise and EMI. Ultimately, we think NCL may also be an important technology component for addressing the larger issues of design reuse and system-on-chip design."

Motorola also is making an investment in Theseus of an undisclosed amount.

Beyond that, Motorola isn't saying much. "We are at a stage in this project where, for competitive reasons, we really are not at liberty to disclose much about it," said a spokesman. "But we feel that over time this will become an important technology."

Theseus founder Fant worked on the underlying concepts for many years while at Honeywell Inc., and he holds the basic patents on NCL. Several white papers describing NCL are available at the Theseus Web site.

Mike Graff, president and chief executive officer of Theseus, said previous attempts at asynchronous logic, largely by Japanese companies, have tapped Boolean constructs, which proved to be a dead end.

By using Null Convention Logic, Theseus has been able to move to a library of large-scale building blocks that are synthesizable using industry-standard synthesis tools. The NCL technology includes an internal latch for three states, representing "data true," "data false" and "no data" (null). It can be implemented as two-, three- and four-value logic and is described as symbolically complete, whereas Boolean logic employs two states: true and false.

Fant and his colleagues developed the algebra, building blocks and architecture for building complete designs that include circuits based on Boolean logic.

"This is logic that is clockless and delay-insensitive and that can be synthesized with conventional synthesis tools, which is important for SoC implementations. It is timeless in a third sense, because it is reusable: Once you design it, it can be migrated and ported to other technologies in industry-standard CMOS," Graff said.

Design teams with conventional circuit designs in CMOS can use those in a "clockless" IC. "From a design point of view, our circuits are described in VHDL building blocks in a clocked Boolean environment," he said. "We have circuit interface logic and methods that allow you to go back and forth between clocked and clockless circuits."

In the military realm, the approach has been used to create digital circuits running at 500 MHz and above.

Graff said delay-insensitive techniques can actually improve performance. "In classical systems, clocks are established to meet the timing requirement of the worst-case delay paths. This is event-driven: When data is ready, you automatically initiate the next event."

Async approaches

"Karl Fant has spent a long time thinking about how to build systems from first principles, independently of the rest of the world," said Steve Furber, a professor of computer engineering at Manchester University and an expert in asynchronous logic. "It turns out that what he has come up with fits into the class of dual-rail delay-insensitive asynchronous logic that is being thought about elsewhere. There are a number of groups that now think this is a way to go."

Furber has pioneered the use of an alternative "bundled data" approach to asynchronous logic and over several years has been applying it in a series of ARM-compatible processors called Amulet.

There are advantages and disadvantages to each approach, Furber said. Null Convention Logic of the dual-rail style tends to be less area- and power-efficient than bundled-data asynchronous logic but has advantages in ease of design because of the implicit timing information.

"With bundled data we use one wire per bit, so for a 32-bit bus you have 32 wires plus one to carry timing. With dual-rail logic you need two wires per bit, and that results in an area bloat of about 100 percent," he said. "Similarly, something as simple as an AND gate is more complex, since you have to propagate the null values as well as ones and zeroes. There is also a lot more activity in the circuits, so there is an issue of power efficiency."

But Furber acknowledged that completing a design and allowing for reuse of cores and subcircuits could be easier with the implicit timing of Null Convention Logic. "We're close to finishing Amulet-III, and we got a lot of timing assumptions in there. Timing closure has been difficult in Amulet-III," he said.

"In terms of electromagnetic interference and electromagnetic compatibility, dual-rail logic should have the same advantages as other forms of asynchronous logic, and in terms of security it has advantages," he added. Furber said he expects to have first silicon on Amulet-III early next year.

Graff said new engineers at Theseus have been able to pick up the approach quickly, but he acknowledged that NCL techniques will require a long learning curve before they are widely adopted. And for design engineers who seek to customize their circuits, knowledge of NCL is essential.

But he said the paradigm shift to SoC design will lead design teams to delay-insensitive design techniques, much as power concerns aided the shift from NMOS to CMOS two decades ago.

"How do we make system-on-chip a reality?" Graff said. "Everyone knows that we are facing a design gap between the number of available gates and the ability to design ICs that use those gates. So we are at an inflection point."

Asked whether the Theseus technology would be used largely in power-sensitive, relatively slow designs, Graff said, "This technology will run as fast as the gates allow us to propagate information. We are not limited by the logic; we are limited by the transistors and, increasingly, the interconnect delays. The variability of timing in a circuit increasingly is dominated by the interconnect and the parasitics. One result is that the timing required to make Boolean circuits work is very difficult."

To manage power consumption, more aggressive gating of the clock — turning it on only when work is done — has trimmed power consumption. But gate clocking adds complexity, clock skew and other design issues, and it's not easy to accomplish, Graff said.

"We think this technology will be key to Internet appliances, wireless comms, all kinds of embedded control," he said.

Angel investors and government research grants have supported Theseus since its inception in 1996. The 30-person company has contracts with half a dozen defense research organizations, including labs at Honeywell and Lockheed Martin.

Theseus is named for the mythical Greek figure who slew Procrustes, an innkeeper who forced all visitors to fit in a standard bed by lopping off their feet or stretching them until they died. The myth stands behind the English word procrustean, or requiring conformance to rigid standards.

— Additional reporting by Peter Clarke