That number could soon reach a dozen, since Xtensa's licensing deals with six other companies are about to come to a close, according to Bernie Rosenthal, vice president of marketing and business development for Tensilica, Santa Clara, Calif.

"We have more licensees working their way through the approval process and expect announcements in the next few weeks," he said.

Tensilica's growing number of licensing partnerships indicates that configurable processing is making its way into many levels of the communications infrastructure, according to Rosenthal.

Fujitsu is Tensilica's first licensee in Japan. "We've been working in Japan for almost a year now, establishing our own subsidiary company," Rosenthal said.

In May, the company formed its first international subsidiary, Tensilica K.K., based in Yokohama, Japan, to target high-volume consumer products.

"We'll be announcing other licensees in Japan," Rosenthal added.

Akria Tsuchiya, general manager of Fujitsu's Circuit and Device Technology Division, said the Xtensa architecture "gives us the unique combination of exceptional performance, instruction-set customization, and DSP capability that we require in our future products."

Santanu Das, president and chief executive of TranSwitch, Shelton, Conn., which provides "connectivity engines" to OEMs serving the WAN and Internet markets, said the architecture will aid its ability to provide "next-generation communications networks. Our solutions will provide customers with a greater degree of flexibility, and greater performance per dollar."

Zilog Inc. announced the first product using the Xtensa architecture earlier this month. Zilog's Cartezian communications architecture combines the Xtensa core with RISC and DSP co-processors, communications peripherals, and software stacks.

"We're ahead of the operating plan we put forward at the beginning of the year in terms of sales, and we're very happy that we seem to be getting a lot of use within the networking space," Rosenthal said.

The Xtensa architecture features a 32-bit RISC-style core with 250-MHz performance at 0.25 micron. Some Xtensa licensees plan to quickly move the processor to a 0.18-micron process that will deliver 380-MHz performance, Rosenthal added.

The core consumes about 0.5 mW/MHz. Options available for the processor include a 16-bit DSP with a 16-bit multiplier, a 40-bit accumulator, a 16-bit hardware multiplier, and a debug module with a JTAG-based interface.