CynApps is also rolling out a VHDL version of its Cyn++ macro preprocessor, which adds a set of macros to CynLib. And the company is unbundling its tools so that users can buy a $25,000 package that includes everything except the company's synthesis offering.

Both CynApps and the Open SystemC initiative, spearheaded by Synopsys Inc. and CoWare Inc., are pushing rival C++ class library proposals. SystemC claims to work at a higher level, incorporating features for representing embedded software as well as hardware. But CynLib claims to run faster on the basis of a simulation benchmark exercise from the Belgian research lab IMEC.

In the report, which was distributed to some members of the Open Verilog International (OVI) architectural language subcommittee, a single RTL design example — a 16-tap FIR filter — is used to compare SystemC and CynLib. IMEC's internal OCAPI C language design environment is also included in the comparison.

While running a four-million clock cycle test bench through the 16-tap FIR, the report states that CynLib ran nearly six times faster than SystemC, at the expense of a slightly longer compilation time. CynLib was also reported to have an executable binary about one-fourth the size of that in SystemC.

Benchmark questioned

But Ivo Bolsens, IMEC vice president, criticized CynApp's citation of the report and stated that it is not meant to be a "professionally executed benchmark." Its goal, he said, was to highlight implementation issues of using C++ for system-level design, and to show how different writing styles and data models can lead to diverse results.

"IMEC does not consider these numbers to be useful as a benchmark to compare the quality of these two environments," Bolsens said. In some other comparisons run by IMEC, he noted, SystemC simulation speeds are on par with CynLib.Pete Hardee, director of product marketing at CoWare, said the comparison was unfair because the SystemC example used arbitrary-length data types. Hardee said these data types, which are unavailable in CynLib, provide more flexibility but incur a speed penalty. When CoWare reran the example using fixed data types comparable to those in CynLib, he said, SystemC simulation speeded up by a factor of six.

Aside from the controversy over the IMEC benchmark, Cyn-Apps does claim to have speeded up CynLib simulation by a factor of two over previous versions due to a new way of implementing threads.

Meanwhile, CynApps is add-ing VHDL-like macros to Cyn++. When using this pre-processor, designers can choose macros such as "entity," "event," and "process."

"With this, a VHDL designer can use our solution to model, simulate and verify an ASIC design," said Jim Cardwell, vice president of marketing and sales at CynApps. However, he noted, the company is not offering a C++-to-VHDL synthesis solution.

To provide potential users with a lower price point, CynApps is unbundling its Cynthesis C++-to-Verilog synthesis tool from its simulation-related offerings. A $25,000 package includes CynLib support, Cyn++ and the Cyntax lint tool. Packages with Cynthesis start at $100,000. CynLib can be downloaded under an open-source license from CynApps.