Finding an off-the-shelf processor that is an ideal fit for an application is becoming increasingly difficult, particularly as embedded systems become more specialized. The advent of configurable microprocessors from companies such as Tensilica Inc. (Santa Clara, Calif.), ARC Cores Inc. (San Jose, Calif.) and Lexra Inc. (San Jose) resolves many of these problems.

These configurable MPUs (CMPUs) are microprocessors that are designed by the provider to meet the exact needs of an application based upon the system designer's specific needs. The CMPU is delivered to the user as a piece of intellectual property (IP) that can be integrated into programmable logic or an ASIC design file.

The actual customization process is different for the different CMPU vendors. Lexra has a number of soft processor cores based on the MIPS instruction set. These cores serve as a starting point, and are modified by Lexra engineers for customer needs. One of the possible modifications is the addition of an optional multiply-accumulate (MAC) unit.

This MAC unit, which can be added to any processor, is provided as an example for how Lexra's Custom Engine Interface (CEI) works. The LX4180P is based on the MIPS 16 instruction set and executes the entire set of MIPS instructions with the exception of unaligned loads/stores. Unaligned loads/stores were useful in data compression in the past, but as memory costs have decreased, the need for compression has diminished, and Lexra chose to remove these instructions to conserve device resources.

In the LX4180P, the optional MAC completes a MAC instruction every cycle. For applications that require higher execution rates such as cell and packet processing, Lexra created the LX4280, which includes a dual MAC that allows for two instructions per cycle. Also, Lexra found that adding common digital signal processing-oriented functions to the MIPS instruction set would better meet the needs of DSP and communications applications, so its LX5280P includes this additional support in a Radiax DSP extension.

ARC Cores and Tensilica each provide a Web-based tool to assist the designers in building their own processors. Tensilica's generator is a Web site with a page-by-page graphical user interface that allows designers to set radio buttons and fill in text boxes based on their architectural needs. ARC Cores' tool provides option tabs which are grouped into the following categories: environment, EDA configuration, instruction-set architecture, cache configuration, memory subsystem, DSP options, debug components and ancillary components. An automated block-diagram-generation capability is available and provides a visual aid to assist in debug. A programmer's model allows a look at the instruction set and the core registers, and is even color-coded so different functions can be identified easily.

Tensilica and ARC Cores both provide starting points for the customized processor. Tensilica allows a choice between a standard 16-bit multiplier or a MAC 16 with a 40-bit accumulator to complement its base processor configuration. ARC Cores provides four different base configurations (a default, a minimal, a DSP and a general), along with a user-defined configuration.

Both Tensilica and ARC Cores allow for custom instructions to be added to the instruction set of the processor. Tensilica's extensions are coded using the Tensilica Instruction Extension (TIE) language, and then rolled into the process generator via a text file. ARC Cores, meanwhile, permits instructions to be coded in VHDL or Verilog and then added into the ARChitect process generator.

Zilog Inc. (Campbell, Calif.) used Tensilica's TIE language to add custom instructions during the design of its Cartezian communications engine. Cartezian was designed to be a combined DSP and RISC processor for communications applications. The heavy signal processing needs of this product required customized instructions to assist with turbo decoding and circular buffering.

The addition of instructions like bit-reversal addressing and modulo incrementing allowed Zilog to provide a more robust and fully optimized product to the marketplace. From Zilog's point of view, Cartezian also has the added security of being implemented with a custom processor. This gives Zilog peace of mind in that no one can duplicate what it did with off-the-shelf products.

Configurable processors are also having an impact on the field of network security processors. With the explosive growth in the communications market and accompanying desire for higher data rates, the demand for high-speed encryption and network security has increased as well. Vendors of network security products are looking toward hardware-based implementations of functions formerly executed in software to increase their performance.

Although hardwired processors can perform well for specific algorithms, they can quickly become obsolete because of the speed with which new encryption protocols are developed. The best solution is a flexible network security processor that can be reprogrammed to handle the latest algorithms-such a solution is only achievable via CMPUs and programmable logic.

A number of other options are available with cores from both Tensilica and ARC Cores, including the number of interrupts and their priorities, the size of caches and memory interfaces, types of peripherals, and the importance of speed, area, and power consumption. In addition, both companies have integrated their processor generators with customized compilers, linkers, debuggers and simulators.

Almost all applications can benefit from cost or power savings by using the custom cache sizes and memory interfaces that products like these supply.