"Within the next 10 years, most logic designs will use [some amount of] programmable logic," and every piece of electronics equipment will have programmable logic inside, Roelandts predicted.

Speaking for Xilinx, but making statements that probably apply to rival Altera Corp. as well, Roelandts built his case on the increasing utility of PLDs—the parts' density, speed and cost are reaching levels where programmable logic can tackle primary logic functions and not just glue logic. In addition, PLD vendors across the board are saying that the increasing expense of ASIC mask sets and shorter time-to-market windows are making programmable logic more attractive to designers, he said.

Still, Roelandts admitted that ASICs will always have a place, particularly for designs that need speeds higher than FPGAs can deliver. Roelandts predicted FPGAs in the year 2004 would reach 50 million gates and 10-metal-layer manufacturing processes. That figure was based on density doubling every two years.

"I guarantee you by the end of this year, you'll see a [Xilinx] chip with 4 million gates," he said.

Copper interconnects are also in the cards for Xilinx. Being blank tablets, in a sense, FPGAs have to connect "everything to everything," resulting in a massive grid of interconnects, Roelandts said. That grid has to go to copper soon in order to keep speeds up.

New software due
In addition to density increases, advancements in software and hard-wired features are in the works for Xilinx's roadmap.

The next generation of Xilinx software is due out in late spring, Roelandts said, and will include a new user interface, a power-estimation feature, and a high-level floorplanning tool. The latter lets a designer place functions into the FPGA as plain blocks, with the software taking care of the place-and-route duties automatically.

Also included will be an internal logic analyzer, which is a debugging feature that allows designers to look at signals inside the FPGA while the part is running.

Software features likely for 2001 include closed-loop synthesis and a block-by-block timing-budget calculator, Roelandts said.

In addition, the trend of adding hard cores to standard FPGAs will continue, he said. Already that's seen in the addition of memory blocks and hard-wired features such as clock management. Roelandts said omre is to come—including, eventually, the embedding of a hard-core microprocessor inside an FPGA, added for the speed of its logic.