The company's Malleable Embedded Communications Accelerator (Meca) combines aspects of highly optimized signal-processing blocks and reconfigurable logic blocks for advanced packet handling.

Malleable Technologies is sampling two versions of its processor for packetized voice: one for voice-over-Internet Protocol (VoIP), and one for voice and telephony over ATM (VTOA).

The chip integrates multiple DSP blocks alongside a TDM-like time-slot indicator, and an asynchronous transfer mode (ATM) cell segmenter/reassembler device. For the VoIP version, the chip substitutes a packet parser and prioritizer for the ATM device.

That range of functions makes Malleable a company whose competitive base spans several markets. By including line aggregation functions on-chip, the company goes up against such communication processor companies as Conexant Systems Inc. and T.Sqware Inc. But Malleable also will have to compete directly against multichannel DSP offerings, particularly as companies like Texas Instruments Inc. absorb telephony software partners like Telogy Networks Inc.

Packetized voice first

Curtis Abbott, founder and chief executive of Malleable, said that packetized voice was merely the first market where Meca architectures would be applied. As software matures for applications such as security and encryption, more processors will be offered for other vertical markets.

The data path cores in the first two devices can handle up to 95 channels of compressed voice. In both versions, Meca-4A for VTOA and Meca-4I for VoIP, users can choose between four different voice codecs to implement in firmware.

The four processing units on the device each consist of an arithmetic unit, an arithmetic-logic unit (ALU) and a reconfigurable logic unit, all operating in parallel. The arithmetic unit handles multiply and multiply/accumulate functions. The ALU is used for adds, subtracts, shifts and compares. The logic unit is reconfigurable on a per-cycle basis, allowing new integer-oriented instructions to be loaded virtually on the fly. Algorithms can then be written in firmware but implemented in hardware for best performance.

Abbott said the logic unit provides the equivalent of application-layer reconfigurability, in that the logic portion of the design resembles a programmable logic device based on logic gates instead of a memory- or antifuse-based FPGA. The unit could be used for such functions as cyclic redundancy checks, header lookups, header formatting, etc.

Malleable vice president of marketing Syed Ali said that the biggest advantage in using such a flexible DSP/integer mix is that the company did not have to stretch process limits to achieve performance gains. The first two packet-voice members of the Meca family are 100-MHz processors dissipating less than 2 watts.

Besides performing ATM Adaptation Layer 2 encapsulation, the segmentation and reassembly (SAR) unit on the chip performs all jitter buffering. The processor interfaces to a host across a 33-MHz PCI bus and to memory through a 100-MHz synchronous DRAM interface.

The Meca-4I offers the same bus interface and firmware options as its ATM cousin, but instead of a SAR, it offers a logic block that performs Internet Protocol header formatting and adaptive jitter buffering.

Malleable is offering an extensive hardware development kit, dubbed Polyphony, based on a CompactPCI chassis. The main board combines the Meca processor with SDRAM memory and multiple PCI bridges, while a separate line card uses PMC-Sierra's 4531 T1/E1 framers for I/O options. A mezzanine card using PMC-Sierra's S/UNI ATM interface chip also is provided.

PMC-Sierra partnership

Malleable maintains a close design partnership with PMC-Sierra. Both companies are offering reference designs for VoIP gateways, VTOA gateways and multiservice access concentrators based on the Meca processor. The processors are used with such PMC physical-layer devices as Apex, Duplex, Atlas and Vortex.

While some in the processor realm have introduced their architectures long before sampling them, Malleable waited until it had silicon in hand before announcing its architecture.

Prices in quantities of 1,000 for the Meca-4I range from $239 to $289 each, depending on the firmware modules. Similar quantities of the Meca-4A are priced in a range of $279 to $329. Both are implemented in 2.5-volt CMOS and are packaged in 27 x 27-mm, 316-pin BGAs. The Polyphony Evaluator Kit is priced at $4,995.