The shifts are indicative of the softening market for high-end 3-D graphics, and beg the question of whether the PixelFusion name indicates too heavy of a graphics center of gravity for the company, which appointed a new chief executive three months ago.

Simon Stanley, formerly of Fujitsu Microelectronics Inc., is heading up product marketing for the networking products group. The latest efforts with the Fuzion processor did not come about solely as a means of expanding its potential markets, Stanley said, but also because several potential customers suggested that the distributed processing and memory array seemed well-suited to multilayer packet classification problems.

Tapeout is complete on the Fuzion 150, and initial prototypes are expected back from the fab within the month. The processor consists of 1,500 simple 8-bit processing elements, each with a private DRAM block, providing a total of 24 Mbits of on-chip memory. The devices are configured in a SIMD array, with a central ARC core playing the role of thread manager. The processor has four Rambus channels on-chip for efficient access to off-chip system memory.

Stanley said that the massive parallelism in the architecture would allow Fuzion 150 to span two classes of traditional network processors. The chip can act as a Layer 2/3 packet parser, where it would analyze the information in Internet Protocol packet headers and organize the packets into flows according to header instructions, similar to the architectures of C-Port, Sitera, and Agere. But the processor simultaneously can serve as a deep packet classifier, drilling into the packet payload and switching packet flows according to the contents of the packet, performing a role similar to specialized chips from Fast-Chip, Solidum Systems, SwitchOn Systems, and Extreme Packet Devices.

Still, PixelFusion executives are cognizant of the limitations of the Fuzion's current implementation. The current bandwidth on I/O channels is unlikely to support 2.5-Gbit/second sustained speeds, though internal bandwidth is 6.4 Gbytes/s. A follow-on processor is targeted at achieving 10 Gbits/s sustained rates, so that it can be used in the type of OC-192 applications targeted by other packet-classifier startups.

The Fuzion 150 also has no interfaces specifically designed for open physical-layer networking standards, so PixelFusion is developing an FPGA which implements both the Utopia interface for Asynchronous Transfer Mode, and the CSIX (Common Switch Interface) spec from CSIX Forum. The latter allows open links to physical-layer switching fabrics from vendors such as Power X Ltd. and Vitesse Semiconductor Corp. PixelFusion has joined both the CSIX Forum and its affiliate, CPIX Forum, which is developing open application programming interfaces to network processors.

PixelFusion already has worked on a variety of C library routines appropriate for graphics manipulation, but Stanley said the company realizes it will need a rich variety of C modules for networking. Consequently, PixelFusion is in discussions with a variety of protocol-stack specialists and third-party software companies to have high-level programming tools ready for Fuzion 150 later this summer.

"We have quite a bit of this software talent in-house, but it became such a time-to-market issue, we had to look outside," Stanley said. "If Fuzion is going to be considered a serious contender among network processors, time is of the essence."