Prolific Inc. (Newark, Calif.) has launched a tool called Liquid Libraries that will create tuned cells on the fly and insert them into the libraries used by place and route tools.

Hot on the heels of Prolific's launch, Cadabra Design Automation (Santa Clara, Calif.) is working on a new flow that would ultimately move library generation as far forward as the synthesis phase, giving logic designers the ability to tune parts of a design for low power consumption or speed.

Both companies have been working on partnership arrangements to bring their tools into the mainstream. Links to the synthesis and place and route vendors are vital for both companies, because the cell generators have to be tightly linked to the layout process.

Prolific is working with Cadence Design Systems, Magma Design Automation, Monterey Design Systems and Sapphire Design Automation. Cadabra is working with Avanti, Cadence, Synopsys and Magma.

Lying at the heart of all ASIC flows, the standard-cell library provides a designer with a fixed set of well-characterized logic blocks. In contrast, designers working with custom methodologies have been able to tune cells to fit individual circuits.

"ASIC and ASSP designs are stuck in the 200-MHz domain but the time it takes to produce chips is small," said Faysal Sohail, president and chief executive officer of Cadabra. "You don't get the best performance or power consumption, but that's the compromise.

"Full-custom [design] has very long lead times in terms of power and performance. In full custom, they can make a transistor do anything they want. The performance gap between these two approaches is continuing to widen rather than closing," Sohail said.

Transistor sizing has become crucial to closing timing, but ASIC designers have limited choices in terms of the number of drive strengths available in any cell library. That often means using cells that are too big and power hungry in a large number of paths where a smaller cell would do. The frequently used alternative is just to add buffers to high-load connections, but that increases power and area.

Custom capabilities, without complexity

By automating the process of generating the libraries, it is possible to provide ASIC designers with the flexibility of custom methodologies without increasing the complexity the flow.

"The key is to go to the core — the building blocks of ASICs are standard cells," said Paul de Dood, president and chief executive officer of Prolific. "Changing the cells themselves is the best way to achieve design goals, not adding buffers."

"In an ideal library, you want a large number of cells per library and you want them to be application specific," said Sohail.

The first fruit of the Cadabra project will be the power and performance optimization (PPO) flow. "We will take the original netlists of designs where they have been placed and routed, but not meeting timing. We can then do optimization at the transistor level," Sohail said.

The second stage will be the Fluid Library. "We are working on a hot-cell generator in which the synthesis tool gives us the requirements it has for cells and we then generate them on the fly," he said.

Although each of the tools will follow the principle of creating cells on the fly, there will be differences in the way they request new cells.

"Some tools, such as Magma's BlastFusion, are able to specify cells. Other tools, such as those from Synopsys, Avanti and Cadence, can't call out a specific cell. They choose them," said Dan Nenni, vice president of sales and marketing for Prolific. "However, you can create a virtual '.lib' [Synopsys' library format] where you can describe cell derivatives numbered in the thousands. If the tool picks a cell that doesn't exist, the tools can generate it."

Cadabra reckons that its PPO software will fit into existing flows. "The flow is the ECO [engineering change order] flow," Sohail said. "You place and route with Silicon Ensemble or a similar tool, then figure out what cells are needed, then create new cells with the same footprint so that the ECO flow can handle them. [This scheme] is showing very promising results."

Prolific also reckons that its approach will be used during synthesis. Prolific's de Dood said that the larger libraries should not slow down the process significantly: "It takes up a small percentage of the total run-time. Generally, you bring in the extended library when paths don't close, he said."

Because synthesis tools generally pick from a list of cells, they will either need to be re-architected or the cell generators extend the idea of a virtual library to that stage as well.

Sohail said, "We can provide a very large number of front-end models for cells that have not been fully generated. The tool can pick from those and we then generate the cells on the fly. The other approach is to rewrite the mapper itself so that the tool can request cells to be produced. We are working pretty closely with Cadence and Synopsys on this and they are quite open to the idea."

Because Magma's BlastFusion tool is built around the idea of dynamically sizing cells to deliver fixed performance targets, the company is working closely with both Cadabra and Prolific.

"It is a necessary move for this type of technology," said Rajeev Madhavan, president and chief executive officer of Magma. "We are working closely with both companies and expect to make some important announcements in a few months."

Because the move toward on-the-fly library generation brings the tools to a wider range of engineers, there will be changes in licensing terms. Cadabra plans to alter its licensing policy for the newer tools, moving to a per-project basis for PPO and to per-seat licenses for Fluid Libraries, the synthesis-oriented tool. The company has already changed the way it sells its library-generation tools to suit situations where a large number of cells need to be generated on the fly.

"We are going more and more to a use-based mode," Sohail said. "Most of our customers buy time-based licenses. When they need to create hundreds of cells, we give them use-based licenses for a short period of time."

— Chris Edwards writes for Electronics Times, EE Times' sister publication in the United Kingdom.