The "Design Closure: Hope or Hype" panel concluded that tools aimed at timing closure do help the average ASIC or system-on-chip (SoC) designer — but are not geared to the needs of engineers who design extremely complex chips. The panel was moderated by Kurt Keutzer, professor of electrical engineering and computer sciences at University of California at Berkeley.

Timing closure refers to the ability of designers to achieve a required level of performance for a chip design. Since this often takes many iterations between synthesis and layout, efforts to facilitate timing closure have spawned a new generation of "physical synthesis" and physical design tools.

Presentations from the seven companies on the panel revealed that tools aimed at timing closure are weighted more towards solving meet time-to-market needs of designers, rather than quality-of-result improvements.

"Compared to 18 months ago, the average ASIC designer is seeing an improvement in how they can tackle timing closure problems," Keutzer told EE Times.

But he added, "The Intels of the world are very lonely because clearly the EDA industry is not focused on building tools for companies creating very large, high speed chips."

As a result, Keutzer said, companies like Intel Corp. (Santa Clara, Calif.) will have to turn to proprietary tools.

Why aren't companies addressing the needs of such designers?

Keutzer believes its because a large microprocessor house, such as Intel, doesn't represent enough design seats to make it worth a company's while to develop tools that are more focused on quality of results.

Rather, EDA companies are focused on mainstream ASIC or SOC designers who must meet time-to-market requirements because they represent a much larger population, he explained.

The panel featured engineering managers and technologists from Synopsys Inc (Mountain View, Calif); Aristo Technology (Cupertino, Calif.); Magma Design Automation Inc (Cupertino, Calif.), Avanti Corp (Fremont, Calif.); Monterey Design Systems Inc (Sunnyvale, Calif.); Cadence Design Systems Inc (San Jose, Calif.) and Sequence Design (Formerly Frequency Technology Inc, Santa Clara, Calif).

Panelists explained their company's approach to design closure, often openly disagreeing with each other on the merits of synthesis-based versus physical-based approaches. Summing up the impact that new physical design tools have had on the industry, the panel determined that improvements offered by the new tools are helpful, but do not offer large enough improvements to spur new companies, nor will they revolutionize the EDA industry.

The new physical design and physical synthesis tools give somewhere around a 10 percent improvement in timing closure, according to Keutzer.

"Engineers will want to add the tools to their toolbox, but they won't be a must-have as they might have been if the potential improvement were greater, " Keutzer said.

EDA companies on the panel learned what engineers think of some of the new tools during the question and answer session. An engineer attending the panel called panelists on the carpet for using the terms "first pass" design close and "zero iterations."

"I'm insulted by the use of the terms 'first-pass' and 'zero iterations' because in my experience with design, that is never true," the engineer said.

"I have used three of the tools represented and all of them said there was no congestion on the chip and that was not accurate."

Asked what he thought of the comments, Keutzer noted that while industry observers can tell the EDA companies what's wrong with their tools, "there is nothing better than hearing it straight from the engineers," he told EE Times.