SAN JOSE, Calif. ( ChipWire -- At the Embedded Processor Forum here today, Tensilica Inc. will unveil its third-generation processor architecture, which moves the company deeper into communications markets with the addition of a DSP coprocessor, called Vectra.
Limited digital signal processor functions were possible in the company's first- and second-generation Xtensa cores, said chief executive officer Chris Rowen. But the Vectra coprocessor, now part of the Xtensa III technology suite, is "not a little upgrade," Rowen said. "It is able to take on the hardest DSP problems, and can be combined with a single processor core or multiple cores."
As CPU vendors move to 0.18-micron technology, the challenge is to complement the increasingly tiny processor cores with flash and embedded DRAM, programmable logic, DSP and other coprocessor functions that bring added value. By adding the DSP coprocessor and widening the on-chip buses from 32 bits to 128 bits, Rowen said Tensilica's technology can be used in applications that require more robust protocol and multimedia data processing. With a robust DSP core as an option, "a whole range of applications will fall to configurable processors," he said.
The Vectra DSP is capable of roughly 400 Mflops. A 256-point fast Fourier transform function requires roughly the same number of cycles as the C6203 DSP chip from Texas Instruments Inc., the company claims.
The additional 25,000 gates for Vectra require about 1.2 to 1.5 square millimeters of die size in a 0.18-micron process. For another 0.5 mm2, floating-point capability can be included. Rowen said the result is "floating-point capability for a dime" -- 10 cents' worth of die area. A 32 x 32 multiplier also can be added.
Tom Starnes, an analyst who tracks DSPs and microcontrollers for Dataquest Inc., said he has no way of evaluating Tensilica's claims for Vectra, and noted that Texas Instruments has moved on to its more-powerful 64X DSP design.
About Tensilica's claim that its DSP core, developed in a configurable approach, is on a par with the dedicated TI62X core, Starnes said, "In some ways you could say that is a fabulous accomplishment, though I have no way of validating that information. And, of course, the core performance is by no means the whole picture. There are still a lot of issues related to getting your C code up and running on a new architecture. When you are starting from scratch, developing software that is rigorously validated can be a challenge."
Tensilica, a well-funded startup that began life in July 1997, offers "automated configurability." Design engineers can select closely coupled peripherals, depending on the application, and add those building blocks in a point-and-click fashion. The processor generator creates a hardware description in about an hour that can be mapped to an FPGA or to process technologies at various foundries.
Rowen said that the resultant Xtensa 32-bit cores and supporting instruction memory are about half the size of an RTL-generation processor core.
The instruction set can be customized by adding Tensilica instruction extensions (TIEs) to the core instruction set architecture. The Xtensa III architecture includes a new TIE compiler, which expands the level of parallelism. The TIE registers and base registers are coupled, providing a basis for "sophisticated coprocessing, coupled to the base machine, that goes way beyond what is available in today's RISC world. We have two sources with one destination," Rowen said.
RTOS environments
Engineers from Wind River Systems Inc. of Alameda, Calif., have worked with Tensilica over the past nine months on an instruction set simulator that brings the Wind River Tornado and ATI Nucleus Plus RTOS environments to the Tensilica architecture. Since the Tensilica designs can be implemented in an FPGA, "this is carrying RTOS capabilities into new areas that use FPGAs," Rowen said.
Also, Mentor Graphics Corp. of Wilsonville, Ore., has brought improved verification technology to the Tensilica architecture.
The Xtensa III-based processor and the co-generated tool environment can be licensed for $350,000. With the Vectra DSP, the price goes to $500,000. For an Xtensa III that includes the Vectra DSP coprocessor, performance typically reaches 320 MHz in an 0.18-micron process, drawing about 0.8 mW/MHz at 1.8 V. With the 0.15-micron process now ramping at TSMC, performance rises to 400 MHz with a 1.5-V power supply.
Thus far, the announced licensees include the Berkeley Wireless Research Center, Cisco Systems, Fujitsu, Galileo Technology, NEC and NTT.
