The company's recent tests using Dow Chemical Co.'s SiLK dielectric material and a spin-on deposition process were disappointing, said Chiang Shang-yi, vice president of R&D for the foundry giant.

"I'm still very concerned regarding the reliability of this process and dielectric," he said. "SiLK works with some kinds of packaging. With others, though, it tends to not bind correctly. There are many concerns regarding how to deal with the packaging issues."

TSMC had originally hoped to make a decision by the end of last month on a low-k dielectric for use at 0.13 micron. Chiang said, however, that he would "rather run two or three research teams now in order to investigate all the possibilities rather than make a hasty decision."

As the world's largest dedicated foundry, TSMC is in the challenging position of having to find a 0.13-micron copper technology that can work across a large group of disparate ICs and packages.

"For Intel or IBM, SiLK will work just fine," said Chiang. "They have fabs dedicated to making just one or two kinds of chips and packaging. But we have to provide services for the whole market. Currently, there are difficulties in finding a dielectric and copper process that can be applied across the whole range of packaging."

TSMC is now commercially producing primarily 0.15-micron ICs with dual-layer copper interconnect using a fluorinated silicate glass (FSG) dielectric. The k value of FSG is around 3.6. The top two layers of interconnect are copper, while the remaining layers use an aluminum interconnect. "I have some hesitation with using a carbon-based organic dielectric, such as Black Diamond," said Chiang. "Silicon-based dielectrics just have a more proven track history."

Full copper interconnect is also offered for the production of ASIC products, and TSMC said that one customer has taped out at 0.15 micron using full copper. In all, eight customers are reportedly using TSMC's 0.15-micron copper process at the tapeout stage.

Qualification and risk production of the 0.15-micron copper process is set for September for two-layer ICs and December for all-copper.

Tapeouts accepted

At the 0.13-micron level, TSMC is now accepting tapeouts for all product lines, including low-voltage and general ICs. For SRAM, low-power 0.13-micron ICs are also in the tapeout stage. TSMC has already demonstrated a high-performance 1-volt transistor made with a 0.13-micron process.

According to TSMC's current timetable, early 0.13-micron production is due to begin in October. Qualification of the 0.13-micron process is set to begin in March 2001. The foundry will use 33 masks for the 0.13-micron process for an IC with eight copper layers. For critical dimensions at the gate, 193-nanometers lithography will be used.