"This changes the cost structure, and is a way to get flip-chip [technology] down in the area of 800 to 900 leads or fewer, into the traditional wire-bonding realm," said Jan Vardaman, principal analyst at TechSearch International, a packaging research firm based here.

LSI Logic's four-layer substrate will be markedly lower in cost than the six- and eight-layer built-up substrates used for high-performance ICs, processors and ASICs. "Flip-chip is not just for the high-performance market anymore," Vardaman said.

IBM Corp.'s Microelectronics Division and other ASIC vendors also have programs under way to reduce flip-chip packaging costs, which have remained high due to limited volumes.

IBM discussed an eutectic solder bump electroplating technology at the recent Semicon West show in San Jose, Calif., and analysts said Big Blue and several other companies are poised to join LSI Logic in offering more affordable flip-chip packages.

Compared with high-lead-count wire-bonded packages, flip-chip offers improved signal integrity to processors, DSPs, SRAMs, chip sets and other cost-sensitive ICs. Rather than use perimeter bonding wires to attach the die to the package, flip-chip places eutectic (a lead-tin alloy) solder bumps across the active side of a die. These are flipped and attached to the package with reflow soldering.

Neil Moskowitz, principal analyst at Prismark Partners (Cold Spring, N.Y.), said flip-chip packaging will be used for graphics, PowerPC processors and other high-performance ICs where costs are important.

"Clearly, flip-chip is becoming cost effective," he said. "It has been used with very low lead counts, three leads or so, in watch ICs and other high-volume applications. And the high end needed flip-chip for the electrical performance and high pin counts. Then there was the no-man's land in the middle, where high costs could not be tolerated. As companies learn how to reduce costs, flip-chip will move to the next big level in terms of growing volumes."

Falling hurdles

Moskowitz, a veteran of IBM's packaging development group, said that "LSI Logic is ahead" in volume flip-chip technology, but that "others will follow as the cost hurdles decline. That will allow companies to migrate from wire bonding to flip-chip."

He said he was unable to elaborate because of nondisclosure agreements.

Stan Mihelcic, technology product marketing manager at the packaging operation of LSI Logic (Milpitas, Calif.), said the company will offer flip-chip packages using a four-layer substrate with lead counts ranging from 365 to 1,157, in package sizes ranging from 23 millimeters on a side to 40 mm. Networking customers are designing ICs now using the FPBGA-4L (flip-chip plastic ball grid array, four-layer) packages, and those products will start volume shipments in March 2001.

LSI Logic has offered customers several types of enhanced plastic BGAs, in which the leads are attached to the BGA package with staggered wire bonding. These "EPBGA" packages have lead counts ranging from 388 to 731 for 1.27-mm solder ball pitch, and up to 928 for a 1-mm ball pitch on the package.

Mihelcic said the four-layer flip-chip package keeps the package bump pitch to 1 mm, but shrinks the die bumps to spacings of 200 to 250 microns, which allows the die size to be reduced in many cases. One network system customer trimmed its die size from 14 mm on a side to 11 mm, he said.

Wire bonding at high lead counts requires such narrow spacings between the wires that performance often suffers because of inductance. For high-speed transceivers, for example, narrow wire leads resulted in unacceptable levels of simultaneous switch output noise. Mihelcic said this kind of noise is reduced by as much as 50 percent with an FPBGA-4L package, which supports 50-ohm signal traces, compared with the wire-bonded enhanced plastic BGA.

Also, the signal waveforms for the 4-L flip-chip are better than with wire-bonded packages. "The square wave we get from the four-layer flip-chip is very much on a par with our high-performance package," which requires a built-up substrate with six or eight layers, Mihelcic said.

The package includes a solid copper heat spreader plane, which he said reduces thermal stress by 40 percent. And printed-wiring boards with only three escape layers (from the package to the board) can be used.

Escape routes

"[Pc-board] design engineers get very nervous when 1,000 pins with very tight ball pitches are used," said Mihelcic. "They may need several layers on their board just for the escape routing, but this four-layer flip-chip supports very efficient escape routing with three layers."

LSI Logic uses the same organic substrate — an epoxy resin similar to the FR4 material used widely in the printed-wiring board industry — that Intel Corp. and others use in their six-layer plastic package substrates.

"Underfill is the key to any plastic substrate today," Mihelcic said.

Indeed, getting a reliable underfill between the die and the package, and doing it quickly, has slowed the migration of flip-chip to the midrange IC realm. Every second, every penny, counts in the back end of the chip business, and slow underfill steps have proved costly.

LSI Logic develops its own packaging technologies and then licenses them to a network of partners. In some cases these partners have provided the LSI-developed flip-chip technology to customers beyond LSI Logic.

For the four-layer flip-chip package, LSI Logic expects that Amkor Technologies (Chandler, Ariz.) will be ready first, using its packaging operation in the Philippines. ChipPac (Seoul, South Korea), Advanced Technology Interconnect (Hong Kong) and ASE (Hsinchu, Taiwan) are expected to license the technology and support LSI Logic customers as well.

Vardaman said the flip-chip infrastructure has expanded greatly over the last few years, with a range of companies providing die-bumping services, microvia substrates for packages, underfills and bonding equipment. Bumping prices have declined as competition among multiple vendors has intensified.

Vardaman said Intel, which shipped some 15 million mobile processors in high-performance flip-chip packages, spurred the market to supply the lower-cost microvia substrates required for relatively high lead counts. Intel's use of microvia substrates for IC packages is expected to increase as the chip giant moves to flip-chip interconnect for all of its CPUs, she said in a presentation at Semicon West last month.

TechSearch International is preparing a report on the flip-chip infrastructure that Vardaman said will be ready by November, priced at $4,000 per copy.

Advanced Micro Devices and Motorola are expected to deliver microprocessors in laminate packages, using microvia substrates, she said, and "virtually all high-end ASIC suppliers are designing microvia substrates for high-pin-count ASICs that will use flip-chip technology. High-end DSPs and chip sets are beginning to ship with microvia substrates as well."

Linda Matthew, a TechSearch International analyst based in Fremont, Calif., said that while companies such as LSI Logic are correct in claiming cost savings for four-layer flip-chip packages, they are reluctant to disclose their package pricing structures. Matthew, who did packaging research for seven years at IBM's center in Yorktown Heights, N.Y., said costs are coming down sharply as "barriers are removed, such as the cost of bumping. There are 16 merchant bumping companies that we know about, which tells you that flip-chip has arrived."