Although price, performance and reliability have limited the proliferation of wireless LANs, a new way of thinking about wireless-system silicon implementation has removed those obstacles.

The challenge of making an order-of-magnitude improvement in the price/performance of wireless LANs (WLAN) requires more than an incremental component redesign. Atheros decided to rethink-and redesign-the entire concept at the system level to make the radio fast, simple and dependable. Driving down cost required developing both the physical layer and media-access control (MAC) in highly integrated, mainstream process technology. The result is the first two-chip, all-CMOS, end-to-end solution, with a complete 5-GHz radio-on-a-chip including an integrated power amplifier, for next-generation IEEE 802.11a standard-compliant WLANs. That standard specifies optional modes up to 54 Mbits/second, but at the high-rate end Atheros chose to implement a proprietary 72-Mbits/s mode that offers better range and speed.

The idea for WLANs is not new and implementations in the 2.4-GHz band have been gaining in popularity. However, the unlicensed 2.4-GHz band has become a maelstrom of competing applications and protocols. What at the time appeared to be an ample swath of spectrum is becoming a contentious area with microwave ovens, cordless telephones, wireless security cameras, wireless local loop systems, Bluetooth personal area networks and WLANs all vying for the same airwaves and interfering with one another in the process.

To their credit, North American and European regulators are in tune with contemporary and future wireless technologies. That's evident in the way regulators have handled regulations at 5 GHz compared with those at 2.4 GHz. At 5 GHz, the spectrum allocation and power rules, along with the absence of microwave ovens and Bluetooth devices, promise a much cleaner environment for WLANs. Further, the industry standard data rate is 11 Mbits/s for 2.4-GHz WLANs under IEEE 802.11b, and 6 to 54 Mbits/s for those using the IEEE 802.11a specification in the 5-GHz band. An all-CMOS, highly integrated chip set can deliver these 5-GHz advantages while driving the wireless price-performance ratio down to levels that will make WLANs ubiquitous in businesses and homes.

Both the U.S. and European regulatory agencies have allocated a 200-MHz portion of the 5-GHz band, from 5.15 to 5.35 GHz, for these types of in-building applications. And both the IEEE 802.11a and European Telecommunications Standards Institute Hiperlan2 standards use the same orthogonal frequency division multiplexing (OFDM) physical layer. Thus, at a radio level both standards are very much alike.

Where they differ, though, is at the MAC level. The IEEE standard uses an Ethernet-like listen-before-transmitting mode of media access; Hiperlan2 specifies the use of ATM-like time slots. Therefore, the MAC implementations for each standard will be quite different.

However, the MAC implementation is essentially a digital one and although it involves complex algorithmic coding, neither the MAC for IEEE 802.11a nor the one for Hiperlan2 is dependent upon a technology breakthrough. But the radio implementation for both clearly required significant innovation.

Extrapolating from the technologies developed to support 2.4-GHz wireless applications, it looked like the cost and power consumption would be too high to support 5-GHz ones. In fact, conventional wisdom suggested it would take three to five years for 5-GHz to become practical because it was too expensive, too energy draining, too limited in range and would not fit on a printed-circuit card. The nature of wireless development has been to treat things discretely-the SAW filter, power amplifier and other RF components are developed independently and without concern for the digital components. As a result, the level of integration has been limited while parts counts, as well as costs, have been relatively high. A major cost driver has been the esoteric technologies, such as gallium arsenide (GaAs) and silicon germanium (SiGe), used to provide the necessary performance.

Without the economies of mainstream semiconductor process technology-that is, standard digital-process CMOS-it looked as if the component costs and therefore the system costs would hinder widespread acceptance of WLANs. Further, it appeared that a CMOS solution would never be achieved because standard-process CMOS has been geared to digital circuits, and 5-GHz RF circuits are analog, requiring large dynamic range and susceptible to noise.

But, in fact, a CMOS solution is possible: not a proprietary CMOS imbued with mixed-signal and analog features, but the mainstream CMOS familiar to manufacturers of 95 percent of the world's digital ICs. What's more, the conventional wisdom turned out to be very wrong. Compared with today's 2.4-GHz solutions, what Atheros developed costs less, consumes one-sixth as much energy, operates at twice the speed over the same range and can be implemented on a single-sided PCMCIA/PC Card. Further, the Atheros radio-on-a-chip is built in 0.25-micron CMOS because our architecture did not require going to 0.18 micron, which is less mature and therefore more costly.

Team effort

The Atheros radio-on-a-chip project has been in development for two-and-a-half years and is the culmination of a team effort involving more than 25 PhD engineers from both Stanford University and the University of California, Berkeley. The Atheros team filed more than 20 patent applications as it attained the initial goals of designing a system that complies with IEEE 802.11a and that is built completely in mainstream 0.25-micron CMOS. Not only that, but in its proprietary turbo mode the device runs up to 72 Mbits/s, more than six times the current generation's 11 Mbits/s.

When the project began the team understood that we would have to live with whatever analog limitations were imposed by CMOS technology: The recipe could not be changed. After all, there are far more foundries building CMOS circuits than any other type of IC technology, and the critical idea was to remain in the mainstream to keep costs down.

We also had to let go of radio-design orthodoxy and approach the solution at a system level rather than a discrete-function level. As a result, the SAW filter was eliminated from our solution and a 5-GHz power amplifier was integrated on-chip. This is significant for two reasons. First, essentially every high-speed power amplifier that has been built to date has been fabricated in GaAs or SiGe. Second, no one else has integrated a 5-GHz power amplifier alongside a low-noise amplifier and other radio functions on a single CMOS substrate.

In typical discrete design these functional blocks or their equivalent physical function areas would all be done individually. In several cases, these functions or equivalents, such as the power amplifier, would be implemented using exotic and expensive technologies, such as GaAs or SiGe.

Here, though, the up- and down-converters, variable gain amplifier, low-noise amplifier, biasing circuit, frequency synthesizer and 5-GHz power amplifier are all on one chip in mainstream CMOS. As described, the companion chip is a digital chip, and CMOS is far more hospitable to digital functions.SEE RELATED CHART CODE:

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