With all the emphasis on custom hardware development, it's easy to forget that much of what differentiates SoC design is embedded software. It may be more important to cleverly code a proprietary algorithm for an ARM processor, or customize an instruction set for a Tensilica processor than to put a lot of time and energy into designing a custom logic block.

Custom hardware is part of most system-on-chip devices, but the people making the key decisions about implementing SoC designs are often coming from a software-centric point of view. Choosing a processor and an RTOS is often the first and toughest task, and there's not a lot of tool support at that level. Once that's done, functionality can be partitioned between software and hardware. What can or cannot be efficiently done in software drives the decisions about hardware.

Today, many large electronics OEMs are outsourcing hardware design. They either purchase cores or hire a design-services firm to create and/or verify custom logic.

It's thus not surprising that startup eASIC Corp. (San Jose, Calif.) chose ESC West to introduce its eASICore, a configurable logic core for platform-based system-on-chip devices. This company's technology combines an SRAM lookup table cell with metal-mask programmable interconnection.

Derivation Systems Inc. (Carlsbad, Calif.) used ESC West to roll out its LavaCore, a configurable Java processor core targeted to the Xilinx Virtex-E FPGA architecture. Xilinx Inc. (San Jose), meanwhile, announced the availability of two packet-over-Sonet (PoS-PHY) cores, while Altera Corp. (San Jose) unveiled technical details of its ARM and MIPS-based Excalibur IP offerings.

On the tool front, U.K. startup Beach Solutions Ltd. announced VHDL and Verilog generator products that let IP designers migrate designs to new bus architectures. And ARM Ltd. (Cambridge, England) upped its debugging support with a multiport trace analyzer.

The hardware-centric Design Automation Conference will always be a major showcase for silicon IP. But people making high-level SoC implementation decisions need to know what's happening on the embedded software side as well.