The past few years have seen explosive growth in demand for RF integrated circuits, fueled by the increased use of cellular phones, the emergence of new or existing standards (such as CDMA and GSM-Edge), and by the introduction of new applications for wireless communications technologies (such as Bluetooth).

This environment offers incredible opportunities to companies developing RF ICs, in the form of both chip sets and individual building blocks. But at the same time, it poses many challenges, such as differentiating products in tight timelines and cost constraints.

One way to tackle those challenges is to employ an integrated top-down methodology to design RF ICs using IBM's BiCMOS6HP silicon germanium (SiGe) process. The methodology provides access to state-of-the-art tools for system- and circuit-level design and simulation, circuit layout, and layout verification, together with accurate RF device models.

SiGe delivers superior performance over standard silicon bipolar processes at a comparable cost level. BiCMOS6HP combines this high-performance bipolar transistor with a quarter-micron CMOS technology, bringing the RF IC and high-density digital content together on the same chip.

That means there's a necessity to combine a circuit design environment with an automated process for creating the physical design and verification of the circuit.

The requirements from a system and circuit design aspect are particularly strict. They demand:

• model interactions of the RF circuits with the rest of the system, including analog and digital baseband signal processing, transmit/receive antennas and signal transmission path;
• model interactions of the desired signal with interfering signals at different frequency and power levels, with different spectral characteristics;
• accurate RF circuit simulations by using accurate device models and proven simulation technologies;
• simulation of the circuit with realistic test signals and realistic measurements on output waveforms;
• and accurate prediction of noise performance and power consumption.

To reduce the number of prototypes, designers must also take into account the effect of parasitics that come into play once the circuit is laid out, and they must perform a final verification on the design before tape-out.

Those factors need to be addressed in an integrated and automated design environment that eliminates unnecessary manual tasks and ensures the circuit configuration is not exposed to accidental modifications that could prompt prototype failures.

The chip set architecture development and the system level trade-off analysis are performed in the ADS environment, using its integrated DSP/RF system/circuit co-simulation capabilities and the built-in libraries for the GSM, CDMA, cdma2000, W-CDMA and Edge standards.

The circuit schematic for each of the functional blocks is then entered in Cadence Composer and simulated in ADS using the RF IC Dynamic Link. That interface allows the instantiation of any number of cells from Cadence DFII on an ADS schematic. Each

of those cells can be then verified using the various available ADS circuit-level simulators, which use time (Spice), frequency (harmonic balance) and modulation (circuit envelope) domain technologies to give a complete view of the electrical behavior of the circuit inoperating conditions. To increase performance and yields, parameter optimization and statistical analysis can be applied throughout the design process.

The performance of the chip set can then be verified by substituting the behavioral definition of each building block with its corresponding transistor-level definition.

To get accurate circuit-level simulations, the devices in the SiGe process have been optimized to operate at RF frequencies, and subcircuit elements have been added to the extracted models to give accuracy across a wide range of geometries, temperatures and frequencies.

Once the performance specifications have been met both at the circuit and system levels, the design is ready for layout. That is done with Cadence's Virtuoso custom layout editor, using parameterized cells.

To verify the performance of the circuit before tape-out, layout parasitics are extracted, and the resulting netlist is then imported into ADS for final verification.

To support this design methodology, the design kit for the IBM 6HP process includes a library of model files for the ADS simulator. This is in addition to the library in Cadence format which consists of symbols, CDF, callbacks and the parameterized cell layout definition. Using this library, the designer can analyze circuits entered in Composer with all the simulators available in the ADS.

The 6HP technology offers two vertical bipolar transistors. The first is a high-performance pedestal npn with a nominal Ft of 47, beta of 100, early voltage of 75 V and BVceo of 3.35 V. The other is a high-breakdown non-pedestal npn with a nominal Ft of 27 GHz, beta of 88, early voltage of 180 and BVceo of 5.4 V. Supported layouts of both consist of single- and dual-emitter stripe devices, with a fixed emitter width of 0.30 mm, 0.42 mm or 0.78 mm. The emitter length can be scaled to obtain the desired current rating.

ADS NPN models use the standard VBIC95 equations. The VBIC model supports weak avalanche multiplication, self-heating approximation, parasitic vertical pnp to substrate, quasi-saturation modeling and improved early-effect modeling.

Extraction of the VBIC models includes S-parameters, noise figure, Fmax and Ft vs. geometry, temperature and bias.

The 6HP technology offers both high-voltage (3.3-V) dual-gate MOSFETs and high-performance (2.5-V) MOSFETs. The 2.5 V FETs have a minimum Leff of 0.18 mm.

ADS models

The ADS MOSFET subcircuits use the BSIM3v3.2 intrinsic model including the non-quasi-static model, extrinsic gate and substrate resistance, the BSIM3v3 thermal and flicker noise equations, device mismatch as a function of threshold voltage and beta mismatch, and threshold voltage correlated to oxide thickness.

The ADS models receive the source/drain diffusion geometry parameters as calculated by parameter callback equations based on the user's geometrical inputs.

The BiCMOS6HP library also includes four resistor types, a metal-to-metal capacitor, a stacked metal-to-metal cap, a scalable spiral (octagonal) inductor, transmission-line device models and a Schottky barrier diode.

The SiGe models in ADS were translated from the IBM HSpice and Spectre models with full functionality replicated. This includes Monte Carlo analysis for statistical simulation. The models have been characterized and extracted from -55 degrees C up to 125 degrees C.

The IBM BiCMOS6HP technology combines a state-of-the-art SiGe bipolar transistor with a 0.25 mm CMOS technology that delivers performance at a cost comparable to that of standard silicon and lower than that of gallium arsenide.

The design methodology described here satisfies time-to-market. The Agilent EEsof tool set gives circuit designers access to some of the world's best simulation engines, such as harmonic balance and circuit envelope, in a design environment that offers an integrated DSP/RF system/circuit co-simulation capabilities plus libraries for GSM, CDMA, cdma2000, W-CDMA and Edge. The design kit provides all the necessary support for linking the IBM 6HP technology and the ADS and Cadence design environments.