The technique puts a new weapon in the chip designer's tool box — the ability to introduce "patterned stress" for enhancing chip fabrication.

"To optimize the performance of smart materials like MEMS [microelectromechanical system] sensors and actuators, we have shown that you can offset residual stress with mechanical stress," said Nancy Sottos, a professor of theoretical and applied mechanics. "I also am working with professor David Payne to use patterned stress on a chip to do additive processing with thin films." Sottos' work on piezoelectrics was performed here with the help of postdoctorate researcher Lei Lian, now with the IBM Research Center (Endicott, N.Y.).

MEMS devices depend on piezoelectric and similar effects to transduce electrical signals into physical motions and vice versa as actuators and sensors. MEMS devices use thin-film piezoelectric effects both for sensors and actuators, in microsize moving devices from ultrasonic motors to switching capacitors.

Ceramics, in general, improve in performance when deposited as thin films. For instance, the brittleness of thick ceramics becomes less of a problem as the material thins out. Unfortunately, the effects of mismatched thermal expansion during firing, densification during cooling and molecular lattice incompatibilities between substrate and ceramic become more troublesome as films get thinner.

Thin film, small response

"Most importantly, we found that both the piezoelectric effect and the dielectric constants of smart thin films depend heavily on thickness — the thinner the film, the smaller the desired response," said Sottos.

To track down the cause and devise a remedy, Sottos and Lian deposited lead zirconate titanate in films ranging in thickness from 0.5 to 2.0 microns. The film's piezoelectric displacements, when electrified, were measured and compared. Since only trillionths of a meter had to be measured, Sottos and Lian used a Doppler laser heterodyne interferometer.

Using Doppler shifts as a carrier, Sottos and Lian were able to accurately measure about a 30 percent decrease in displacement between the half-micron and 2-micron films. The measurement was made by reflecting an argon laser beam off a 4-MHz acousto-optic modulator, then splitting the beam along the two arms of the interferometer. One beam bounced off the sample, while the other served as the reference.

When the two were recombined, the Doppler shift atop the 40-MHz carrier signal indicated the displacement of the thin film.

To alleviate residual stress between layers, Sottos and Lian applied an oppositely oriented mechanical stress. When that external stress was applied after the fabrication of the chip, it was found to compensate for the residual stress effect of processing the very thin films.

"We can greatly improve the performance of MEMS devices by optimizing their smart materials to relieve stress, and by adding mechanical stress to offset residual stress," said Sottos.

Doing "stress management" for smart materials starts with identifying all the sources of stress — from the intrinsic stress caused by shrinkage and densification during drying and firing the chips to the extrinsic stresses induced during cooling because of mismatch between the thermoelastic properties of adjacent layers. The thinner the film, the larger the proportion of its surface stress to its total mass, thereby introducing even lattice mismatches between ceramic and silicon, further degrading piezoelectric displacement.

Luckily, both intrinsic and extrinsic stresses in thin films can be compensated for by applying a mechanical stress in the opposite direction to overall tensile stress. Applying enough stress to relieve just 10 percent of the tensile stress resulting from fabrication regained the expected 30 percent loss in the displacement of the piezoelectric element, as measured by Doppler effect. Thus mechanical stress can cancel out altogether the negative effects of residual chip stress.

Cool out

"There are certain things you can do to keep stress from building up in the first place, say by changing the way you cool a chip after firing it," Sottos said. "You can also apply a mechanical stress during fabrication that could potentially be removed once the chip cooled."

Sottos is also investigating ways of harnessing residual stress during fabrication to enable additive chip fabrication. Together with Payne, she has patterned a special polymer atop silicon using traditional lithography, then put a thin film atop the patterned polymer. Residual stress between the polymer and the thin film makes the film flake off over the polymer, leaving only the "addition" of the patterned film over silicon.

Because the film flaked off with very clean edges, Sottos and Payne have already secured funding to perfect the process as a chip fabrication technique.