At the Semicon Southwest show held Oct. 17-18 and sponsored by Semiconductor Equipment and Materials International (SEMI), sources said the severity of the problem is causing several premier chip companies to reevaluate their interconnect programs for high-performance 130-nm process technologies. At the same time, potential solutions to one aspect of the problem — the difficulties that low-k dielectrics pose for chemical mechanical polishing — emerged at the show. One startup, ACM Research Inc., unveiled an electropolishing technology that would replace the CMP steps required to planarize multiple layers of interconnect.

Among the chip companies said to be revisiting their options is Texas Instruments Inc., which initially selected Applied Materials Corp.'s Black Diamond low-k dielectric. Asked for an update on TI's interconnect strategy, a TI manager said only that the company plans a public announcement in the near future.

"Many of our colleagues also are still scrambling around," the TI manager said. "It is causing us some pain, but I'm sure we will solve it."

Paul Winebarger, the interconnect program manager at International Sematech, said the complexities of replacing silicon dioxide — which is hard, inert, transparent and thermally stable — are causing headaches throughout the industry.

The 130-nm process technologies are due to begin commercial production next year. "Normally, by now, [chip vendors] would have long ago disclosed their choices for a low-k material. The fact that they are this late is an indicator of just how sticky the low-k process integration issue has become," Winebarger said.

IBM Corp.'s Microelectronics Division may be the only major company that made an early commitment to a low-k material — the SiLK dielectric, from The Dow Chemical Co. — and that has worked through the process integration steps for its 130-nm technology.

"With respect to 130-nm low-k technology in general, I would not describe the situation as a technology wall, but rather an expected evolutionary development of these materials," said Bob Havemann, International Sematech program manager for copper and low-k integration. "Certainly, some people may have been overly optimistic, but the materials are coming along and will be introduced into products in due time."

One core problem is that most of the replacements for silicon dioxide are relatively soft and require capping layers. As the interconnect stack is subjected to high temperatures and to the mechanical stress of chemical mechanical polishing, defects are induced.

Though the organic dielectrics will need a capping layer, Havemann said, the challenge of integrating the low-k materials with CMP can be resolved. "For the porous low-k materials being considered at the 100-nm [0.1-micron] node, CMP is definitely an issue, and a capping layer is necessary to prevent serious erosion and low-k damage from photoresist ashing. Silicon carbide is the leading candidate for the capping layer since it has good CMP resistance," said Havemann, who recently contributed a detailed analysis of the low-k challenge to EE Times.

Hydra-headed problem

But Winebarger said CMP is just one aspect of a Hydra-headed problem. For a material with a dielectric value of 2, the challenge is to keep the k value that low as the wafer moves through the various process steps. Since the new materials are not inert, the k value tends to rise, degraded by the high temperatures and by reactions to the chemicals used in the etch and clean steps. Further, the capping and barrier materials have high k values, raising the dielectric value of the overall insulation stack.

"What can start out as a k value of 2 can end up as a 3," Winebarger said.

The issue is not just an arcane technical debate, he said. As the semiconductor industry moves away from the happy marriage of silicon and silicon dioxide, process steps become more complex and costs spiral upward. To cut the resistance-capacitance (RC) delays, the industry has no choice but to move to copper wires — and to difficult-to-handle materials to insulate wires that are being placed ever closer together.

While companies can try to cope with the problem by keeping critical wires short, spacing out wires more efficiently and other "front-end loading" design techniques, the traditional improvements in performance depend heavily on being able to wire transistors together fairly easily and cheaply.

Some companies, such as Intel and LSI Logic, will put off the shift to low-k dielectrics, sticking with a fluorinated silicon dioxide insulator for the 130-nm generation. To keep performance moving upward in the 100-nm generation, companies must shift to materials with aggressive low-k values — materials that tend to be even more porous and to exhibit poor mechanical strength.

Generally speaking, Havemann said, the use of CMP will become more "a significant challenge" with the porous ultralow-k (< 2.5) materials.

"The use of a dummy metal for structural support helps, but one still has to contend with shear forces. The adhesion of the capping layer [with the dielectric] appears to be the weakest link," he said.

Several approaches have been suggested that would reduce or replace CMP steps. AlliedSignal Inc. and Austria's SEZ Group are working on a cleaning process that would remove chemical films without CMP.

And at Semicon Southwest, ACM Research (Fremont, Calif.) discussed its electropolishing technology as a replacement for CMP. But its equipment probably won't be ready until process technology hits the 100-nm generation in three years, said company president David H. Wang (not to be confused with the Applied Materials executive David N.K. Wang).

ACM's Wang is a native of China who did graduate work in Japan from 1984 to 1990. While at Osaka University, Wang learned about the use of electropolishing technology in the automotive industry. After leaving Quester Technology (Fremont) in November 1997, he developed a method of locally controlled electropolishing, in which small sectors of the wafer are polished in what is essentially an etching process.

Electropolishing, in which an electric current stimulates an etching action across a surface, had been studied for use in the semiconductor industry and then dismissed. Wang said a Lawrence Livermore Laboratory team had concluded in 1993 that electropolishing could not be extended to work for copper films that were thinner than 1,500 angstroms (1.5 microns).

One problem was that polishing evenly across the surface of the wafer required a relatively high current, of about 40 amperes. Also, it was difficult to place the anode and cathode so that the resistivity would be held constant between the edge of the wafer and the center region. And for very thin films, the voltage tended to vary from the edge to the center, resulting in overpolishing in the edge region.

"The standard thinking was that electropolishing was no good," Wang concluded.

But the ACM research team developed a system that locally controls the current, dividing the wafer into small sectors. The wafer is immersed in a proprietary chemistry — an acid that is relatively inert until a voltage is applied. The system design — the chamber, control software, chemistry and other parts of the puzzle — were optimized for localized control.

ACM also developed a copper electroplating tool that uses a localized approach to depositing very thin copper films. As the trenches and vias in a metal stack continue to shrink, ACM is betting that its copper electroplating approach will win out.

Crucial ally

Herb Henderson, one of the original staff at Applied Materials, worked with Wang at Quester Technology. Henderson was in semiretirement when Wang called and "sold me on the localized plating technology, which I believe can be applied to [plating on] very thin seed layers," he said.

ACM — which is backed by several angel investors — has developed prototype tools for both the electroplating and electropolishing systems. Though it may be six months or so before fully finished machines are completed, ACM is working with several semiconductor companies to evaluate the approach.

"The real issue is not the technology; that has been demonstrated to work," Henderson said. "The question now is what is the most effective way to commercialize the technology — whether that is with a strategic partner, in one form or another, or in a potential merger."

ACM, Henderson said, must find an OEM for the equipment whose reputation will "guarantee that the end customers feel good about the support."

Asked whether he had approached his former employer, Applied Materials chief executive officer Jim Morgan, Henderson said only that he has "kept in touch" with Morgan over the years.

Wang said ACM's patent applications have been favorably reviewed by the U.S. Patent Office. While the patents have not yet been granted, he said, the examiner has informed ACM that no prior art has been found.

He said he expects the patents to be granted soon.