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When RISC, DSP coexist








EE Times


Will StraussThe conventional thinking was that if you were a DSP house, you had more than enough horsepower to do less processor-intensive, RISC-like data processing. And if you were a RISC house, you bolted a multiplier-accumulator (MAC) on and you just knew that you could take on the DSP guys. But there are drawbacks to the "I can do it all" approach.

First and foremost is the division of labor. The programmer who does all of the C-language data processing is usually ill-equipped to handle the necessary assembly-language signal-processing tasks.

Likewise, the rare breed of software engineer or algorithmist who can write the most compact modem modulation code probably has no love for Java-which may also be required in an Internet appliance application.

Second, DSP support tools for RISC engines are usually abysmal; so are the C-language support tools for DSP chips. Third, processor architecture differences-like the ever-deeper pipelines of RISC-can actually negatively impact the execution of some DSP code.

But if we look at the most successful single application for DSP, it's also the most successful application for RISC.

Virtually all of the 400 million cellular handsets forecast to ship this year have both DSP and RISC cores, usually on the same die. The RISC core takes care of all of the nonreal-time call-handshaking functions. The DSP core does the real-time signal processing for the basic communications functions like speech compression.

The two live happily together, usually as an ASIC tailored for a given cell phone manufacturer, and are likely to do so, well into the coming third-generation market.

But there are many more opportunities for coexistence, either on the same die or as separate chips. The soon-to-boom market for integrated access devices (IADs) for voice-over-Internet Protocol and voice-over-DSL is another case where the pairing makes sense. Licensable IP-telephony protocol stacks (like H.323, Megaco and SIP) are usually available only in C, favoring a RISC engine. With rare exceptions, if the IAD is to support more than four channels, a separate DSP engine makes the most sense, since the speech compression and associated tasks dominate the processing budget.

Many other markets also favor such coexistence. If pairing both RISC and DSP on the same die makes good sense, why haven't we seen such a combo chip on the open market? Watch this space.

Will Strauss is an analyst with Forward Concepts (Tempe, Ariz.), a research firm specializing in the Chip Industry.










The views and opinions expressed in this column are strictly those of the author and should not be taken as an editorial position of EE Times or any of its other editors, publications or Web sites.


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