Panelist Jim Ballingall of United Microelectronics Corp. said at 0.13-micron a typical die (1 cm²) will be extremely dense and accommodate 20 million gates. "Roughly 70 percent of that will be memory, but that leaves 5 to10 million logic gates." Designing five to 10 million gate designs in shrinking product windows bodes to be a tough task for design groups.

And panelist Guy Doupenloup, director of ASIC design methodologies at LSI Logic Corp., said physical design engineers faced with 0.13-micron designs are going to need solutions that make them far more productive than they are today.

Doupenloup said that power integrity and excessive IR drop, crosstalk and timing failures are becoming more commonplace as designs move from 0.18-micron to 0.13-micron. "We are fixing up to 100 crosstalk failures in 0.18-micron designs and at 0.13 it will become an even greater problem," he said.

"At 0.18-micron, more digital signals are going to start behaving like analog signals," said panelist Saili Ponnapalli from CadMOS. "To deal with this, physical effects are going to have to be taken into account at higher levels of abstraction. At the RT level now, you have to take into account parasitic and deep submicron effects."

Doupenloup and Ponnapalli said that power, signal integrity and timing are becoming ever more interrelated at 0.13-micron and that fixing a power problem could for example mean violating a signal integrity or timing rule.

Doupenloup called for "avoidance solutions" — tools that would guide routing and account for these effects throughout the design process.

Doupenloup said that the company has used a variety of new timing closure tools and that quality needs to improve greatly.

"We are finding bugs in these tools, and it causes productivity to go down — some of these bugs are showstoppers," said Doupenloup.

Doupenloup also called for better test methodologies, especially to move high-pin-count devices onto low-pin-count testers.

Numerical Technologies' Atul Sharan said that at 0.13 micron, it will be mandatory that physical design tools be phase-shift- and optical-proximity-compliant.

The problem according to Sharan is that with 193-nm steppers two years away from hitting the market, the industry now on precipice of using 0.13-micron is faced with the issue of making feature sizes smaller than the wavelength of light used to produce the feature sizes.

Sharan said that OPC and phase-shift tools allow manufacturers to use 248 steppers to do finer geometries, but that to ensure designs don't get caught up at mask development, physical design tools now more than ever will have to become phase-shift-compliant.

Bob Payne, vice president and general manager of system ASIC technology at Philips Semiconductor, said that incorporating a plug and play reuse methodology will not cut it for a 10-million-gate design.

"A lot of people say the solution is to store away design objects, call them out of a library and piece them together and do a 10-million-gate design by piecing together 100,000-gate blocks," said Payne. "An ARM7TDMI is 40,000 gates, so piecing together one hundred 100-gate objects is a very difficult thing to apply."

Payne drew upon an analogy saying that successfully completing a design with one hundred 100-gate blocks was much like the probability of a good fighter pilot completing 100 combat missions.

"Ever wonder why there are very few fighter pilots that have completed 100 combat missions?" he said. "If they are good, they have a 99 percent probability of returning. After you fly 100 missions, the likelihood that you are alive is 37 percent. This is very similar to applying one hundred 100-gate complexity reuse objects. You can argue with the numbers and the analogy, but unless the success rate is in the upper 90s of probability of success, we have a serious problem. To reach time to market, we have to bring these numbers well into the 90th percentile."

To get there, Payne said, designers will likely have to adopt rapid silicon prototyping methodologies, in which several fundamental blocks — MPUs and DSPs — have already been merged into a sort of macro core that can be easily modeled and verified with formal verification techniques. Payne said differentiation of products based on the methodology will be done mainly in software but also through links with other cores or perhaps platforms.