When I first heard about Superlog two years ago during a DAC party, I thought that Simon Davidmann was pulling an EDA party joke on me. Here he was, a Brit who lived over eight time zones away from Silicon Valley, and he was going to be the CEO leading "the next Verilog revolution" in the HDL world.

In my DAC Trip Report, I parodied Simon as the Joe Isuzu of that year's DAC. Within 10 months, I was apologizing to Simon in print in a subsequent SNUG Trip Report because a number of veteran chip designers I respected were expressing a serious interest in Superlog.

Now some 18 months later, after the recent Boston SNUG, Anders Nordstrom of Nortel e-mailed me: "The most interesting part of Aart de Geus' keynote address was what he did not talk about. He did not mention SystemC at all. Most of the focus was on timing closure and how Physical Compiler is going to help you with both timing closure and crosstalk. When asked, he mentioned SystemC for verification, but said it is important not to get into a language war such as the one with Verilog and VHDL and therefore you should use C. Strange, when there are SystemC, C-level and SpecC, to mention a few. Now we have five, instead of two languages, if you do not count Vera and E. My vote for verification language still goes to Superlog, since it is an evolutionary path from what we do today coding Verilog. Ideally, I want all Superlog features in Verilog so I can truly have one language for design and verification."

Steve Start of AMI responded and added, "Anders said he preferred Superlog over C. I agree. Superlog looks like the better way to go. It's geared toward SoC as a one-language solution and simplifies aspects of SW/HW co-design because design teams use a common language. Being a superset of Verilog, it incorporates some of the more-powerful constructs of C while allowing use of older proven design blocks or IP written in Verilog."

And at the Boston SNUG conference itself, Kurt Baty had made a remark that all Superlog really needed was a synthesis tool to make it design-usable.

So what may be its key selling point is that the Superlog revolution isn't revolutionary at all. Unlike Vera or C/C++ hardware design, using Superlog doesn't mean you have to start over by throwing away all your old legacy Verilog code. "The beauty of Superlog as I see it is that it is an evolutionary path from Verilog," Anders concluded. "I can start out with 100 percent Verilog and then add as much Superlog as I want. Superlog has some very useful constructs such as structures, queues, re-entrant tasks, protocol checkers and pointers which are lacking in Verilog."

The more things change, the more they stay the same.

John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a contract ASIC designer, and loves hearing from engineers at (jcooley@world.std.com) or (508) 429-4357.