Gathered here for the giant Electronica trade show, top guns from STMicroelectronics, Philips Semiconductors, Infineon Technologies and Motorola pointed to the huge opportunities and accompanying risks involved in system-on-chip (SoC) design. To cope, what's needed is "a scalable, standard platform on which our customers can flexibly combine features to build systems," said STMicroelectronics' Philippe Geyres.

The challenge of designing next-generation SoC devices no longer lies in integrating millions of gates but in clever system-level partitioning, said Geyres, corporate vice president and general manager of the consumer and microcontroller groups for the French chip giant.

In illustrating a Pocket Multimedia Platform under development at STMicro, due for rollout in mid-2001, Geyres said, "To design such a power-conscious platform, by far the most important thing is the right partitioning." Using low-power cores and processors will bring the design just so far. More important, Geyres said, is system-level partitioning — issues like off-chip and on-chip memory, memory access, bus bandwidth and I/O.

The Pocket Multimedia Platform — designed for mobile phones with multimedia capabilities or for consumer boxes combining portable digital audio players with handheld games or digital cameras — will offer a wide variety of features, he said. They include camera functions, access to the Web, multimedia capabilities to handle up to MPEG-4 encode/decode, wireless communications and good image processing for a small display.

"Since nobody knows the specification of a portable device with the winning combination of features, OEMs will need a flexible and scalable platform to develop their software and hardware," said Geyres. "They will also need to get their solutions quickly to market."

The platform idea was one trend that emerged last week as chip executives discussed strategies for coping with big, fat SoC devices. For Arthur van der Poel, president and chief executive officer of Philips Semiconductors, the pay-off lies in taking SoC integration into the interconnection realm. Van der Poel claimed Philips already has a lead in this area with its Nexperia consumer platform.

For his part, Hermann Eul, vice president and general manager of Infineon Technologies AG, said the Munich-based chip maker has devised a two-pronged design methodology. Applications are rendered in hardware by Infineon; separate from that is the software platform, enabling flexibility for standards and protocol changes, and the like. "We clearly separate these two levels," Eul said. "It gives the customer flexibility and also speeds design."

"ICs used to be designed for standalone boxes," said Philips' van der Poel. "Then, more and more SoC [devices] in recent years have been developed for connected boxes such as cable set-tops. But now we are beginning to see SoC designed for 'interconnected' systems."

Under a connected-home scenario, where devices are expected to interconnect and interoperate, a cable box may need to talk to a PC via 802.11, while that same PC may also hook up to a GSM phone via Bluetooth, said van der Poel. That's when the architecture originally designed for a consumer environment must cross-fertilize with PC or telecommunication environments, he said.

Sea of architectures

Moving beyond "sea of gates" and "sea of IP [intellectual property]," the semiconductor industry today is facing "sea of architectures," he said. In designing new-generation SoC devices over the next five to 10 years, the challenge lies in figuring out ways to reuse architectures, van der Poel added.

Leon Husson, general manager and executive vice president of Philips Semiconductors, said the company's Nexperia platform alone will need to be implemented at least in three architectures depending on where a Nexperia device is used: at home, in a car or outdoors.

As consumers start demanding ubiquitous services such as real-time video, digital audio, Internet access, data communication, banking, games or time-shifting wherever they are, chip vendors face "a huge surge" of SoC demands, he said. Such devices must be designed to offer infinite combinations of features.

"In the convergence world, service providers conduct many new experiments with many new boxes on the marketplace," said Husson. "Nine out of 10 boxes will fail." No single chip company has the time or R&D resources to develop point solutions for each and every one of them, he said.

Particularly important in the reuse of architectures for SoC is the management of software. For the semiconductor industry, software still tends to be somewhat of an afterthought, Husson said.

"We at Philips don't intend to become an independent software vendor, but we can't be a buyer of a plain-vanilla middleware designed by third parties, either," he said. "We need to get access to middleware source code so that we can embed it in our SoC solutions for our customers." Husson pointed out that Philips is focused on the development of key software stacks such as the Digital Video Broadcast standard's Multimedia Home Platform, MPEG-4 and HAVi.

The SoC era will bring many architectural changes. "The densities on silicon that we will have means we will have to look at how systems are architected," said Fred Shlapak, president of Motorola Inc.'s Semiconductor Products Sector, who foresees an architectural sea change. "We will see down the road a lot of distributed processors on one chip." Yet he called design "the greater challenge" facing chip makers today. "We will have to verify monsters," Shlapak said. "They will be multiengine, multibus, multimemory, multi-mixed-signal and multi-OS, all on the same chip.

"They will have to be tested, verified and simulated. Extrapolations of existing technologies won't work. The devices will have to be self-testing and self-healing, with more redundancy," he said.

Shlapak also pointed to the challenge, on the manufacturing side, of shifting to 12-inch wafers. "What types of function will be produced in the first few years of 12-inch?" he asked. "Memory, processors and some very high-volume wireless silicon." But he added: "Eight-inch fabs will live for a long time. Anyone doing 12-inch will have to have very good business models. And the good candidate products are the 'uniproducts,' such as the Intel Pentium, DRAM and flash."

In Shlapak's view, the other main candidate is the new class of reconfigurable architectures. "If you could build reconfigurable architectures that could run in high volumes, then they would fit [12-inch manufacturing]," he said.

Shlapak also said he is looking forward to innovation in memory, and pointed to Motorola's research in magnetic RAM as an example. By contrast, van der Poel said that Philips doesn't see its lack of a memory business "as a serious handicap. We fell flat on our face in the memory business. We see memory as a devil's business, where you make profit for three years and at the fourth year you are forced to give everything back."

Van der Poel said that Siemens, as well as Philips Semiconductors in a joint venture with IBM, have already tried embedding memory with logic. "And we found very few applications where this was useful." In his view, logic embedded in flash or DRAM will not be a breakthrough in the semiconductor industry.

— Additional reporting by Peter Clarke and Brian Fuller. Chris Edwards is editor of Electronics Times, EE Times' sister publication in the United Kingdom.

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