A team of Intel researchers led by Robert Chau used 248-nm lithography with phase-shift masks, silicon dioxide for the gate oxide, and other conventional technologies to create the test transistors, said Gerald Marcyk, director of components research at the Hillsboro, Ore., facility of Intel Labs. The test circuits operated at 0.85 volt.

The junction leakage was "reasonably low," at less than 1 nanoampere per micron at 1-V operation at 100C for both n-MOS and p-MOS, according to the IEDM paper.

Several research teams from major semiconductor companies have concluded that scaling the gate oxide of silicon dioxide may be the toughest challenge facing solid-state technology. Thus, papers from IBM Corp. and others at IEDM, which starts here today, will look at new high-k materials that deliver the electrical performance of a thin SiO₂ layer but prevent electron tunneling by providing a thicker physical gate oxide layer.

The Intel Labs team used silicon dioxide that was a mere 3 atoms (8 angstroms) thick, Marcyk said. "Part of the reason people thought we would hit a brick wall with CMOS scaling was that reliability concerns [arise] over gate oxide leakage. From this research, we have gained an understanding of how to make gate oxides with acceptable leakage currents."

He added that Intel has made progress with new gate oxide materials that may be used when the 70-nm process technology goes into manufacturing in 2005.

"We may have some high-k gate materials ready by 2005 that give the same capacitance with lower leakage," Marcyk said. "The research going on is encouraging."

Intel used a new electrical measurement technique, based on distributed capacitance, to explore the gate oxide performance of the test circuits. The technique, developed by a team led by Doug Barlage, was described in the September issue of IEEE Electron Device Letters.

Intel expects to use extreme-ultraviolet (EUV) lithography to print the critical dimensions, with 157-nm tools as the predominant workhorse at the 70-nm node. "The current thinking is that we can use 157-nm lithography for everything except the gate, which is a 30-nm dimension. For CD [critical dimension] control, we want to introduce EUV."

Fast as speeding bullet

The 70-nm process will let Intel build 10-GHz microprocessors containing 400 million transistors. An Intel press release said such microprocessors could "finish 2 million calculations in the time it takes a speeding bullet to travel one inch."

In the more prosaic language of the IEDM paper, Chau wrote that the devices have an n-MOS gate delay of 0.94 picosecond and a p-MOS gate delay of 1.7 ps at the 0.85-V operating voltage. The n-MOS drive current was 514 µA/micron; p-MOS drive current was 285 µA/micron.

Marcyk said Intel generally tries to keep its process as simple and straightforward as possible to control costs and maximize yields. Moving to a nonplanar CMOS structure, such as the vertical replacement gate being developed by a Bell Labs team, may be needed at some point, but not at the 70-nm node, according to Marcyk.

Likewise, Intel's current thinking is that moving to silicon-on-insulator technology would introduce unneeded process complexity, for little or no performance gain.

While Intel, with its enormous volumes, has tended to stick with tried-and-true materials as long as possible, IBM's Microelectronics Division has driven its process technologies into untested realms to meet the bleeding-edge performance needs of its servers.

At IEDM, IBM researchers will present work on integrating a true high-k gate dielectric with lifetimes that may exceed the stability of silicon dioxide. The Al₂O₃ used was the only significant change to an otherwise normal CMOS device, with a gate length of 80 nm, which corresponds to the 130-nm (0.13-micron) technology node.

While some research teams continue to investigate a wide variety of metal oxides, based on zirconium, hafnium, titanium and lanthium, the IBM paper suggests that the company may have narrowed its search for a high-k dielectric to the aluminum oxide, which could be employed at the 100-nm node and beyond when SiO₂ runs out of gas.

The Al₂O₃ film has a dielectric constant of 11, far better than the roughly 4 k-value of SiO₂. Use of transistor gate oxides with an effective electrical thickness of less than 1.5 nm kept gate leakage currents 100 times lower than for the equivalent silicon dioxide films.

Moreover, the reliability of the aluminum oxide is "as good, if not better, than that of SiO₂," wrote D.A. Buchanan of the IBM research team. The group compared 10-angstrom (1-nm) SiO₂ films with 15-angstrom (1.5-nm) Al₂O₃ films.

The Al₂O₃ film was grown using low-temperature, atomic-layer chemical vapor deposition. The thicker films keep electrons from tunneling through the material, while the higher k value supports the good electrical performance that a thin gate oxide delivers, according to the team.

Reliability remains a major topic. Investigators at IBM, Osaka University and elsewhere argue that electron holes can damage gate oxides after extended use.

More IEDM coverage.