In their drive to market broadband cable to everyone, a key challenge for the major cable system operators was to get together and develop a standard method of implementing high-speed data services across the industry. Such a method would encourage many manufacturers to develop standard subscriber and head-end products; the cost benefits of high-volume production would accrue to both the multiple system operators (MSOs) and subscribers. Moreover, standard subscriber products could lead to a consumer retail business model for cable modems similar to that of traditional dial-up modems.

So the cable industry created its own technical specification called the Data over Cable Service Interface Specification, or Docsis. Cable Laboratories Television Inc. (known as CableLabs), a research and development group for the industry, administers the standard and ensures interoperability among vendors and equipment types.

Over the past two years, many MSOs in the United States and elsewhere began to deploy Docsis-based, high-speed data services. These deployments were based on the Docsis 1.0 version of the specification and first-generation system platforms from various vendors. In the United States alone, more than 3 million households will actively be using high-speed data services by the end of 2000, multiplying year after year into the future. Many of the large MSOs in the United States and Canada are currently providing broadband cable modem service, including Adelphia, AT&T, Cablevision, Charter, Cogeco, Comcast, Cox, Media One, Rogers, Shaw, Time Warner and Videotron.

These first-generation implementations have delivered great value to the industry by validating the specification, the technology and the marketplace. However, as residential applications and usage continue to increase and as consumer lifestyles become more dependent upon high-speed links to the home, the demand for highly reliable service and higher performance will continue to increase. MSOs increasingly require high-reliability and high-availability infrastructure, including new-generation cable modem termination systems (CMTS).

More services
As the industry matures, the need to offer a broader range of services to meet the needs of emerging market subsegments also increases. As a result, a new version of the Docsis specification was developed to provide for differentiated services and new applications such as IP-based telephony. This new version is Docsis 1.1, which defines a minimal set of quality-of-service (QoS) features that must be maintained by all compliant CMTS products, as well as advanced QoS features that are recommended (but

not required) for CMTS products. Most computer networking products (switches and routers) have already added some elements of QoS to their feature sets. While different standards committees are still deciding which of several different QoS proposals will be formally adopted for the Internet, QoS can be implemented now in head-end equipment that provides cable data services. The consequent improvements in service performance are especially evident in the presence of increasing cable traffic. The change for the Internet is important because it will transform the current Internet routing model from "best-effort" service for all users to one where different types of packets and traffic flows are treated differently. Within a cable data network, the latter model can be implemented today.

When QoS is enabled in a ubiquitous end-to-end fashion across the Internet, it will be possible to deliver differentiated services with assurances of corresponding performance. High-priority packets will be routed with low latency and low jitter; low-priority packets may experience more delay and more jitter. The throughput needs of different applications will determine the priorities associated with their corresponding traffic flows for both cable head-end processing and Internet transit. It is even likely that advanced application programs will be able to dynamically change the priority associated with the application's traffic flows during program execution.

Since all packets will not be processed using the same level of priority, it follows that different billing rates can apply to different classes of packets-based on service level requested, delivered or both. Future Internet users are likely to pay differently for different classes of service and they may be billed on a usage (per-minute, per-packet or per-byte) basis. As differentiated billing is adopted, service-level agreements (SLAs) between subscribers and their service providers will detail the available priorities, their associated costs and the relevant warranties of performance. Such changes in service delivery and in the billing model represent substantial revenue-generating potential for MSO access providers.

MSOs are located at an optimal place in the cable network architecture to act as the gatekeepers for priority services. They have access to each subscriber's service-level contract and can appropriately mark the priority of all packets that are injected into the Internet by their subscribers. In fact, an MSO's equipment is the first trusted equipment (not owned by the subscriber) through which subscriber packets must pass on their way to the Internet.

An MSO is responsible for customer subscription packages and is able to offer and bill for different levels of subscriber service. In addition, when head-end CMTS permit, the MSO will be able to offer dynamic service-level upgrades to its subscribers. To be successful in this new model, the MSO must be able to meter the usage of different service levels by time and packet or data volume, and by cable modem or computing device behind each cable modem. The principal revenue-generating QoS capabilities will be provided by features contained within an MSO's CMTS, which is positioned at the head-end office, where it provides basic connectivity between the cable plant and the Internet.

In general, a feature-rich, QoS-enabled CMTS will provide for packet classification, packet prioritization, per-flow policing, congestion control, flow control, fine-grained queuing, scheduling and per-flow traffic shaping. To perform these QoS functions without degrading CMTS throughput, hardware-assisted QoS processing (wire-speed processing) is generally required. A CMTS design capable of wire-speed processing will be able to complete all the QoS functions plus all the functions associated with forwarding, counts and measurements in less time than the shortest expected interpacket arrival time. Without wire-speed processing, these functions can take longer than the interval between two successively arriving packets. Then, the CMTS must queue the second packet while finishing the processing on the first one. Over time, the queue's depth will grow and service-affecting packet drops will result; subscribers will perceive a lower grade of service-lower throughput, lower bandwidth, less response. The result would be a loss of customer satisfaction.

MSOs may therefore prefer CMTS products that offer QoS functions via wire-speed processing. With the high data rates found in the Internet today, there are only a few practical methods to achieve wire-speed processing. One method is to design high-speed, custom ASICs to implement the special QoS processing. This approach is costly and the resulting ASICs are difficult to modify in an evolving-standards environment. Another method to achieve wire-speed processing within a CMTS is to pipeline the processing functions using techniques similar to those used in an automobile assembly line, with each stage of the pipeline performing only a subset of the entire task. Subtasks are concatenated and new tasks (packets) can be fed into the pipeline at a very rapid rate.

Pipelining can be implemented in software, hardware or some combination of both. Pipelining via software can be done with high-speed processors, which benefit from relatively fast development times, a large array of development tools and a widely understood development environment.

Unfortunately, most general-purpose processors are limited in task partitioning and bus flexibility. A new generation of network processors attempts to address these disadvantages by executing network tasks via parallel processing, although their ability to handle real-time data such as voice and video traffic is relatively unproved. Also, it remains to be seen if data dependencies, as well as tasks like scheduling and managing, can be handled efficiently by the software compilers for network processors. In hardware, pipelining can be achieved via programmable logic, which avoids the long development times of ASICs and provides much greater speeds than pure-software approaches. Hardware-level performance is especially important because standards like Docsis are likely to increase low-latency demands on packet transport. Additionally, many modern PLDs include architectural features that are good for CMTS designs, including high-speed I/O buffers, phase-locked loops (PLLs) and flexible embedded-memory structures.

A balanced design approach that combines programmable logic and high-speed processors can yield the benefits of both implementations, including the performance of hardware acceleration, the familiarity of a software development environment and the flexibility of a reprogrammable platform.

Reaching higher speeds
The latest programmable-logic devices (PLDs) support a number of I/O standards and voltages. By allowing multiple I/O voltages, these PLDs can be used as interfaces between other components on the board, ranging from 1.8 V to 2.5 V and 3.3 V. More important, high-speed I/O options such as low-voltage differential signaling (LVDS) allow PLDs to reach much higher performance levels, as high as 840 Mbits/second per channel. These speeds are achievable because of their combination with on-chip PLLs, which perform clock multiplication on the serial-to-parallel converters.

By combining the PLLs and LVDS, a designer can increase the bandwidth of the system. For example, consider a switch fabric element with eight clients, two buses per client, eight I/Os per bus and no LVDS-PLL combination. The total number of I/Os is:

8 clients x 2 buses/client x 8 I/Os/bus = 128 I/Os.

If the clock speed is given as 50 MHz, the total throughput is:

128 x 50 MHz = 6.4 Gbits/s.

Next, consider the system with the same system clock and the same number of clients with an LVDS-PLL combination. The total number of I/Os is:

8 clients x 4 buses/client x 2 I/Os/bus = 64 I/Os.

64 I/Os equals 32 LVDS pairs (which can be clocked at 8x the system clock by the PLLs), so the total throughput is:

32 LVDS pairs x 400 MHz = 25.6 Gbits/s.

This result indicates that the LVDS-PLL combination results in a fourfold throughput increase over the non-LVDS-PLL version of the switch fabric.

The on-chip memory that many modern PLDs feature can be used in a number of CMTS-related functions. In the most advanced PLDs, the on-chip embedded-memory blocks can be configured into various memory functions, including FIFOs, RAM, ROM and content-addressable memory (CAM). CAM is useful for symbolic compression and cache tagging and can also be used in payload header suppression to perform tree-search algorithms that look up suppressed header patterns. In cases where the size of the on-board CAM is inadequate, the PLD vendor provides reference designs to help interface to larger, external CAM devices.

By combining a PLD's on-board memory blocks with the clock-multiplication capabilities of the PLLs, several useful Docsis-related functions can be created. For example, dual-clocked FIFOs can be used to store incoming Ethernet frames and convert them to 8- or 4-bit widths as necessary. In this case, an input clock writes the 16-bit frames into the FIFO and a 2x or 4x version of the input clock reads the data out into a 2-to-1 or 4-to-1 mux (also controlled by the multiplied clock), which outputs 8-bit or 4-bit values.

A dual-port RAM combined with a PLL can provide clock domain transformation, where data is written to the RAM with one clock and read out with a multiplied version of the clock.

Finally, a PLL and a dual-port RAM can also perform data manipulation like single-cycle read-modify writes, where a FIFO is written to at twice the rate it is read from. On every other write clock cycle, unmodified data is written to the FIFO; on the other write clock cycles, the data is read out, modified with a mask value and written back.

The expected advances in programmable logic, including higher performance, more and faster I/O, increased memory and, of course, greater density will keep PLDs well-suited for cable modem processing tasks.

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