Larry Pileggi doesn't believe all the differentiation in this wave of platform design is going to be implemented in software. Pileggi doesn't believe that nothing in the ASIC flow will change, either. Instead, Pileggi, a leader in one of the most visionary think tanks in the world of chip design, is taking a hard look at silicon. Gigascale silicon, to be exact.
In fact, while some groups at the Gigascale Research Center (GSRC) are looking at how to create application-specific reconfigurable architectures so easy a software designer can program them, Pileggi's group is examining the trade-offs in affordability vs. performance for implementing gigascale silicon.
With costs of gigascale silicon, especially chip mask sets, heading for the millions of dollars, most companies are expected to use one application-specific silicon platform for several generations of products, then differentiate those products with software.
But Pileggi doesn't think that will be the optimal solution in all cases because silicon keeps evolving.
Pileggi, for his part, is a noted professor in the department of electrical and computer engineering at Carnegie Mellon University, director of the Center for Silicon System Implementation (CSSI) at CMU and head of the GSRC's Constructive Fabrics Theme.
"Every generation product is going to be in a new technology," said Pileggi. "You can no longer just take a quarter-micron design with your reconfigurable logic and shrink it down to 0.10 micron without all sorts of problems breaking loose. Because of the manufacturing reality, someone will have to painstakingly design that SIP (silicon implementation platform) for that technology, including the tools to program it and the tools to design the ASIC."
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| One of the goals of Larry Pileggi's Gigascale Research Center is to span the gap between customizable and programmable silicon. |
The GSRC Fabrics Theme's vision is to create and support SIP design methodologies that provide a continuum of reuse vs. customization trade-offs. The ultimate goal is to span the gap between fully customizable to fully programmable fabrics.
An SIP, according to Pileggi, is a single IC or multichip package comprising a partially customizable architecture with a defined communication protocol and specific components that are generally associated with a particular application domain.
"One of the big things we are trying to do is make it affordable for people doing ASICs today to add hardware differentiation in the future," said Pileggi.
Pileggi said that finding the right mix for your application between fully customizable ASICs and fully programmable will be key.
"I think everybody is recognizing you can't simply dump some very high-level description of what you want a system to do into a blender and out comes your silicon," he said. "We are trying to stake out a middle ground and say what we can do instead of having one programmable platform. We believe many of them will offer things like programmable or reconfigurable systems but also allow a certain amount of customization where that makes sense."
Pileggi said the GSRC Fabrics Theme, which is roughly one year into its 10-year mission, is currently tackling two issues: silicon effects modeling and building tool algorithms to handle those effects appropriately. "We are doing a lot of modeling work to understand the realities of manufacturing. That allows us to do two things: determine what should be prefabricated into the SIP or what can be represented by design rules at the system level," said Pileggi.
The GSRC Fabrics Theme is looking at better modeling of physical effects such as cross-coupling and power effects.
Pileggi said that once the structure for implementation is built, the group can propose the algorithms in synthesis and methodologies to develop a speedy application-specific tool set that will facilitate system-level design.
"We need to build better models of physical effects, but then you have to abstract them at the synthesis level," said Pileggi. "In the past, we built our synthesis tools from the top down. We now are working on synthesis algorithms that are more open. So when you compare it to a particular synthesis tool that has been optimized to a particular technology, it won't do as well, but, being more general, it can incorporate more physical reality models more easily."
"But being more open, it also can adapt to a new technology," he said. "SIPs are going to have these flows associated with them, but you don't want to rewrite a synthesis tool for every SIP."
"You want to have a synthesis module that could be reconfigured for new technologies," he said. Pileggi said it is very likely that many of the tools for those new platforms will come directly from silicon vendors who know their silicon strengths and weaknesses and can place them in application-specific tool suites. "I'm a bit of an optimist though," said Pileggi. "I think there is going to be a lot of work done through cooperation between silicon vendors and traditional EDA vendors."
