Last year, Intel appeared ready make a full disclosure on its much-anticipated McKinley processor, the follow-on to Merced that some analysts believe will be the real shining star of the IA-64 architecture.

In an early advance program issued last year by the IEEE Solid-State Circuits Society, the organizer of ISSCC, Intel was scheduled to make a presentation on what it described as "the second implementation of the IA64 architecture" with 214 million transistors based on a six-layer metal (aluminum), 0.18-micron process technology.

The architecture is described as having a seven-stage pipeline and third-level cache hierarchy implemented in four separate arrays. The caches are separately optimized for latency, bandwidth and density, according to the pamphlet.

An Intel spokesman said the company wasn't ready to make a full disclosure when it decided to pull the paper. ISSCC requires presenters to provide in-depth detail about their designs, he said.

Intel has been sampling its first IA64 processor, dubbed Itanium, since last year for test and evaluation. One source at an OEM said Itanium development has been slow, but that the first systems have been demonstrated and "our hardware and software are making good progress." Earlier problems Intel had in getting Itanium out the door did not cause serious disruption because the custom ASICs needed for Itanium systems were still under development, the source said.

An Intel spokesman did not respond to a query from EE Times on when Itanium is expected to ship in volume.

Linley Gwennap, president and chief analyst of the Linley Group, said he expects Itanium to start shipping by midyear. "The test cycles on these systems are ferociously long," he said. "McKinley should go faster because there should be a lot of infrastructure and software."

Gwennap said the expectation is that McKinley will go into pilot systems this year, and move into production systems next year. "I wonder if this ISSCC thing means it's slipped beyond that," he said.