BLACKSBURG, Va. — Synapticad Inc. said it is offering the first tool able to generate SystemC testbenches from language-independent timing diagrams. The company's TestBencher Pro 7.2 graphical testbench-generation tool includes support for SystemC, an emerging system-level design language.
TestBencher Pro produces cycle-accurate, bus-functional models from timing diagrams, Synapticad said. The latest version can produce SystemC, Verilog or VHDL code. Version 7.2 also generates state and timing protocol checkers to verify the response of the model being tested.
"We evaluated a lot of languages, and we liked SystemC as a system-level language," said Donna Mitchell, vice president of marketing at Synapticad, who said the company was receiving a lot of requests for SystemC capability. "If you're doing software and hardware design, you can actually simulate both together at the same time. It provides a unique high-level test environment."
Synthesis options
Given the lack of available synthesis tools, prospective users still need to go to Verilog or VHDL for synthesis, Mitchell said. But that's no problem, she said, since TestBencher Pro can generate Verilog or VHDL from the same diagrams used to produce SystemC.
Synapticad's main rival, Chronology Corp., announced SystemC support last year but hasn't yet fielded a product. Chronology merged with CynApps Inc. in March to form Forte Design Systems. Cynapps has developed the Cynlib C++ library, a rival to SystemC.
TestBencher Pro's "sampling" construct can check the state of a signal at a given point in time, or over a window of time. The product also supports "sequence recognition," which allows a sequence of states to be defined for a timing diagram. The generated testbench can trigger off of that sequence whenever it comes up during simulation. TestBencher Pro 7.2 is available now on Unix and Windows platforms starting at $15,000.
