Ron Smith, senior vice president and general manager of Intel's Wireless Communications and Computing Group, showed a 340-MHz version of the DSP core, operating at 1.3 V. Smith showed the core performing speech-processing functions running an adaptive multirate algorithm.

While Intel's first evaluation board ran at 170 MHz — more than fast enough to handle emerging 2.5G applications — Smith said Intel has already had the core running at over 400 MHz at 1.6 V in the lab.

"We didn't want to stop at 170 MHz, because we wanted to create headroom for 3G. Cell operators are banking on a lot of data," he said.

Another feature of the architecture is dynamic power management, which optimizes the task at hand by adjusting the voltage and frequency. Tuned instructions optimize the bit stream for multimedia applications.

Considering the wireless-handset focus for MSA, power consumption at a given performance level was a focal point for the development team, which comprised engineers from Intel and co-development partner Analog Devices Inc. "The data they're showing for the demonstration ranges from 0.7 V at 0.11 milliwatts per million multiply-accumulates, or MMACs up to 0.64 mW/MMACs at 400 MHz and 1.6 V," said Dennis Sheehan, director of marketing for Intel's Cellular Communications Division. "The configuration is designed to fully consume the system."

The power figures are just for the core itself, but Smith said that Intel aims to replicate that performance in full devices.

The most important speed feature of the architecture could be the time-to-market edge it imparts. Because MSA is optimized for C/C++ programming, Smith claimed the architecture could collapse months or years of hand-packing coding into days or weeks. "This architecture overcomes the basic barrier and opens coding up to a whole class of C programmers. This means that other DSP technology is pretty ancient," Smith told EE Times.

Time-to-market unknown

Meanwhile, MSA's own time-to-market remains an official secret, as do the identities of the OEMs that have expressed interest. Smith declined to comment on when Intel will integrate the core with logic and then ship DSPs based on the architecture. He would say only that the company will make an announcement later this year.

"It's still very much a development project," Sheehan said of MSA. "The silicon is basically a test chip for the core; it's not a product yet."

While co-developer Analog Devices will aim at general-purpose DSPs and the discrete market, Smith said, Intel will target wireless baseband chips and integrated systems-on-chip packing both MSA and XScale, Intel's RISC solution for application processing in wireless handsets.

The Tokyo demo came a week after Intel Capital helped 3DSP Corp. (Irvine, Calif.) raise $24 million in 3DSP's latest round of financing. Details of the Intel investment were unavailable. But 3DSP chief executive officer Tom Beaver said the Intel investment validates his company's technology and road map, which has the company scaling its SP5 32-bit, fixed-point, five-multiply-accumulate (MAC) DSP core to a 20-MAC version.

The DSP will target wireline voice-over-Internet Protocol and Internet gateway applications.