BLACKSBURG, Va. — Providing some of the first third-party tool support for the OpenVera hardware verification language, SynaptiCAD Inc. has rolled out TestBencher Pro version 7.4, which generates OpenVera testbenches from timing diagrams. The language-independent tool also supports Verilog, VHDL and SystemC.
When Synopsys Inc. announced the open-source OpenVera language in early April, SynaptiCAD was among some 20 third-party endorsers — and one of two companies cited by Synopsys as having announced product plans. The other is Denali Software, which supports OpenVera with its Memory Modeler product.
SynaptiCAD has been working with Synopsys for about 18 months on the OpenVera support, said president and chief executive officer Dan Notestein. The Vera language, he said, "has some nice constructs for modeling things that are difficult to do in VHDL or Verilog."
TestBencher Pro provides a graphical environment for generating testbenches from timing diagrams, using a bus-functional modeling approach. The product's goal, said Notestein, is to provide a tenfold speedup in the time it takes to develop testbenches. TestBencher Pro claims to let users build testbenches without having to learn language features, and to more easily share data across projects.
In addition to speeding testbench development time, Notestein said that TestBencher Pro can help OpenVera users build better testbenches. "It's very easy to write testbenches that have subtle problems in them," he said. "The most common problem you see is race conditions. We generate the stimulus in a way that won't produce race conditions in the code."
Notestein said users can "pretty much" do everything with TestBencher Pro's graphical notation that they can by writing OpenVera code, although there are a few exceptions. "If you want to write a function that computes an answer on a bunch of numbers or data, you're better off writing that in straight native code," he said.
To use TestBencher Pro, Notestein said, users write some top-level code anyway. They can also write code functions that are called from within the graphical environment, making it possible to mix timing diagrams with code.
TestBencher Pro currently does not support full-functional models, however. Notestein said SynaptiCAD is "looking into" generating full-functional models in the future, but for now, TestBencher Pro generates either bus-functional or high-level "transactor" models.
The OpenVera testbenches generated by TestBencher Pro need to be compiled by Synopsys' Vera testbench automation tool. They can then be used with any major commercial Verilog or VHDL simulator.
TestBencher Pro 7.4 is currently available on Solaris and Windows NT platforms starting at $15,000 for single-language support.
